CM6533-N Datasheet, PDF (41/60 Pages) C-Media Electronics – USB 2.0 Full-Speed compliant

CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
6.9 SPI Interface
The SPI interface is used to transfer control data between the CM6533/CM6533N/CM6533X1/CM6533DH and external
codec.
In a SPI interface there is only one central clock source producing a reference clock to which SPI data processing is
synchronized. This clock is often referred to as the MCU clock, e.g. for SPI clock 12Mhz, When the MCU clock equal
48Mhz and SPI clock div4.
6.9.1 SPI Control Register 0
Address: 3ch
Bits R/W
7 R/W
6 R/W
Bit Mnemonic
slv_mst
long_mode
Description
SPI master/slave mode
0: master mode
1: slave mode
SPI slave address length
0: 1-byte address
1: 2-byte address
5
--
--
Reserved
4
--
3 R/W
2 R/W
1 RO
0 RO
--
si_mode
si_mode_rs
flag_rd
flag_wr
Reserved
Serial interface mode
0: normal SPI mode
1: Serial interface mode
Serial interface RS/A0 output
0: RS/A0==0 for 8^th bit
1: RS/A0==1 for 8^th bit
Flag read
0: mcu can’t read spi data
1:mcu need to read spi data
Flag write
0: mcu can’t write spi data
1:mcu need to write spi data
default
1’b1
(POR)
1’b1
(POR)
1’b0
(POR)
1’b0
(POR)
1’b0
(POR)
1’b0
(POR)
1’b0
1’b0
6.9.2 SPI Control Register 1
Address: 3dh
Bits R/W
7 R/W
6 R/W
5 R/W
Bit Mnemonic
spi_start
spi_lh_edge
Spi_flash_rd_wr
Description
Trigger SPI read/write command
0->1: trigger SPI read/write command.
1->0: SPI interface had completed current task.
0 : SPI interface is idle and ready for work.
1 : SPI interface is running.
SPI CEN control
0: codec latch control data at SPI clock low (default)
1: codec latch control data at SPI clock high
SPI Flash Read/Write
0:spi flash read (default)
1:spi flash write
default
1’b0
(POR)
1’b1
(POR)
1’b0
(POR)
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