CM6533-N Datasheet, PDF (36/60 Pages) C-Media Electronics – USB 2.0 Full-Speed compliant

CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
0
R
i2c_ctrl_reg2
Slave NACK error occur
1 : No error
2 : Slave NACK error occur
1’b0
(POR)
*Note: Write-MAP-Only: An operation which only writes the register MAP the salve device
6.8.9 I2C Master Download Control and Status Register
Address: 0x95
Bits R/W
Bit Mnemonic
Description
7 R/W
RO
6
WO
5:4 R/W
3
RO
2
RO
1 R/W
0 R/W
I2c_mas_sel
Flag_8byte
Flag_ready
LD_BLOCK
CHKSUM_ERR
CHK_FINISH
CHK_PHASE
LD_PHASE
I2C master/slave select
Flag_8byte (RO): Flag to status I2C is
transmitting at 1^st 8 bytes data or 2^nd 8
bytes data.
If the flag index it’s transmitting the 2^nd 8
bytes data, then F/W can prepare the next
8 bytes data into 1^st 8byte buffer.
Flag_ready (WO): Flag to index F/W has
prepared next data ready.
After prepare done, F/W need set this bit
to index the data had been written. If F/W
didn’t catch on when all data has been
transmitted, the I2C clock would be keep
low to till it ready.
Download to which block of SRAM.
00: Load to 1^st 8KB block.
01: Load to 2^nd 8KB block.
10: Load to 3^rd 8KB block.
11: Load to 4^th 8KB block.
Check sum Error
1. If in LD_PHASE, the check sum
value was calculated by I2C load
data.
2. If in CHK_PHASE, the check sum
value was calculated by SRAM read
content.
CHECK phase done
1: finish download data CHECK
MCU select CHECK phase to read SRAM
data for check-sum check.
1: enable (after disable LD_PHASE)
0: set 0 after complete
MCU select LOAD phase to access SRAM
from download.
1: enable
0: set 0 after complete
Default
1’b1
(POR)
1’b0
(POR)
2’b00
(POR)
1’b0
1’b0
1’b0
(POR)
1’b0
(POR)
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Rev.1.6
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