CS42448_07 Datasheet, PDF (50/64 Pages) Cirrus Logic – 108 dB, 192 kHz 6-In, 8-Out CODEC

6.10 DAC Channel Invert (Address 10h)
7
INV_AOUT8
6
INV_AOUT7
5
INV_AOUT6
4
INV_AOUT5
3
INV_AOUT4
2
INV_AOUT3
CS42448
1
INV_AOUT2
0
INV_AOUT1
6.10.1 Invert Signal Polarity (INV_AOUTX)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
6.11 AINX Volume Control (Address 11h-16h)
7
AINx_VOL7
6
AINx_VOL6
5
AINx_VOL5
4
AINx_VOL4
3
AINx_VOL3
2
AINx_VOL2
1
AINx_VOL1
0
AINx_VOL0
6.11.1 AINX Volume Control (AINX_VOL[7:0])
Default = 00h
Function:
The level of AIN1 - AIN6 can be adjusted in 0.5 dB increments as dictated by the ADC Soft and Zero Cross
bits (ADC_SZC[1:0]) from +24 to -64 dB. Levels are decoded in two’s complement, as shown in Table 15.
Binary Code
0111 1111
···
0011 0000
···
0000 0000
1111 1111
1111 1110
···
1000 0000
Volume Setting
+24 dB
···
+24 dB
···
0 dB
-0.5 dB
-1 dB
···
-64 dB
Table 15. Example AIN Volume Settings
6.12 ADC Channel Invert (Address 17h)
7
Reserved
6
Reserved
5
INV_AIN6
4
INV_AIN5
3
INV_AIN4
2
INV_AIN3
1
INV_AIN2
6.12.1 Invert Signal Polarity (INV_AINX)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
0
INV_AIN1
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DS648F3