CS42448_07 Datasheet, PDF (34/64 Pages) Cirrus Logic – 108 dB, 192 kHz 6-In, 8-Out CODEC

CS42448
4.5.7 I/O Channel Allocation
Interface
Digital Input/Output Format
I²S, LJ, RJ
DAC_SDIN1
OLM
TDM
I²S, LJ, RJ
DAC_SDIN2
OLM
TDM
I²S, LJ, RJ
DAC_SDIN3
OLM
TDM
I²S, LJ, RJ
DAC_SDIN4
OLM
TDM
I²S, LJ, RJ
ADC_SDOUT1
OLM
TDM
I²S, LJ, RJ
ADC_SDOUT2
OLM
TDM
I²S, LJ, RJ
ADC_SDOUT3
OLM
TDM
Analog Output/Input Channel Allocation
from/to Digital I/O
AOUT 1,2
AOUT 1,2,3,4,5,6
AOUT 1,2,3,4,5,6,7,8
AOUT 3,4
Not Used
Not Used
AOUT 5,6
Not Used
Not Used
AOUT 7,8
AOUT 7,8
Not Used
AIN 1,2
AIN 1,2,3,4,5,6
AIN 1,2,3,4,5,6; (2 additional channels from AUX_SDIN)
AIN 3,4
Not Used
Not Used
AIN 5,6
Not Used
Not Used
Table 9. Serial Audio Interface Channel Allocations
4.6 AUX Port Digital Interface Formats
These serial data lines are used when supporting the TDM Mode of operation with an external ADC or
S/PDIF receiver attached. The AUX serial port operates only as a clock master. The AUX_SCLK will operate
at 64xFs, where Fs is equal to the ADC sample rate (ADC_LRCK). If the AUX_SDIN signal is not being
used, it should be tied to AGND via a pull-down resistor.
The AUX port will operate in either the Left-Justified or I²S digital interface format with bit depths ranging
from 16 to 24 bits. Settings for the AUX port are made through the register “Interface Formats (Address
04h)” on page 44.
4.6.1 I²S
AUX_LRCK
AUX_SCLK
AUX_SDIN
MSB
Left Channel
Right Channel
AUX1
LSB
MSB
AUX2
LSB
Figure 21. AUX I²S Format
MSB
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