CS42448_07 Datasheet, PDF (3/64 Pages) Cirrus Logic – 108 dB, 192 kHz 6-In, 8-Out CODEC

CS42448
4.11 Power Supply, Grounding, and PCB Layout ................................................................................ 38
5. REGISTER QUICK REFERENCE ........................................................................................................ 39
6. REGISTER DESCRIPTION .................................................................................................................. 41
6.1 Memory Address Pointer (MAP) ..................................................................................................... 41
6.1.1 Increment (INCR) .................................................................................................................. 41
6.1.2 Memory Address Pointer (MAP[6:0]) ..................................................................................... 41
6.2 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 41
6.2.1 Chip I.D. (CHIP_ID[3:0]) ........................................................................................................ 41
6.2.2 Chip Revision (REV_ID[3:0]) ................................................................................................. 41
6.3 Power Control (Address 02h) ......................................................................................................... 42
6.3.1 Power Down ADC Pairs (PDN_ADCX) ................................................................................. 42
6.3.2 Power Down DAC Pairs (PDN_DACX) ................................................................................. 42
6.3.3 Power Down (PDN) ............................................................................................................... 42
6.4 Functional Mode (Address 03h) ..................................................................................................... 43
6.4.1 DAC Functional Mode (DAC_FM[1:0]) .................................................................................. 43
6.4.2 ADC Functional Mode (ADC_FM[1:0]) .................................................................................. 43
6.4.3 MCLK Frequency (MFREQ[2:0]) ........................................................................................... 43
6.5 Interface Formats (Address 04h) .................................................................................................... 44
6.5.1 Freeze Controls (FREEZE) ................................................................................................... 44
6.5.2 Auxiliary Digital Interface Format (AUX_DIF) ........................................................................ 44
6.5.3 DAC Digital Interface Format (DAC_DIF[2:0]) ....................................................................... 44
6.5.4 ADC Digital Interface Format (ADC_DIF[2:0]) ....................................................................... 45
6.6 ADC Control & DAC De-Emphasis (Address 05h) ......................................................................... 45
6.6.1 ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE) .................................................. 45
6.6.2 ADC3 High Pass Filter Freeze (ADC3_HPF FREEZE) ......................................................... 46
6.6.3 DAC De-Emphasis Control (DAC_DEM) ............................................................................... 46
6.6.4 ADC1 Single-Ended Mode (ADC1 SINGLE) ......................................................................... 46
6.6.5 ADC2 Single-Ended Mode (ADC2 SINGLE) ......................................................................... 46
6.6.6 ADC3 Single-Ended Mode (ADC3 SINGLE) ......................................................................... 47
6.6.7 Analog Input Ch. 5 Multiplexer (AIN5_MUX) ......................................................................... 47
6.6.8 Analog Input Ch. 6 Multiplexer (AIN6_MUX) ......................................................................... 47
6.7 Transition Control (Address 06h) .................................................................................................... 47
6.7.1 Single Volume Control (DAC_SNGVOL, ADC_SNGVOL) .................................................... 47
6.7.2 Soft Ramp and Zero Cross Control (ADC_SZC[1:0], DAC_SZC[1:0]) .................................. 48
6.7.3 Auto-Mute (AMUTE) .............................................................................................................. 48
6.7.4 Mute ADC Serial Port (MUTE ADC_SP) ............................................................................... 49
6.8 DAC Channel Mute (Address 07h) ................................................................................................. 49
6.8.1 Independent Channel Mute (AOUTX_MUTE) ....................................................................... 49
6.9 AOUTX Volume Control (Addresses 08h- 0Fh) .......................................................................... 49
6.9.1 Volume Control (AOUTX_VOL[7:0]) ...................................................................................... 49
6.10 DAC Channel Invert (Address 10h) .............................................................................................. 50
6.10.1 Invert Signal Polarity (INV_AOUTX) .................................................................................... 50
6.11 AINX Volume Control (Address 11h-16h) ..................................................................................... 50
6.11.1 AINX Volume Control (AINX_VOL[7:0]) .............................................................................. 50
6.12 ADC Channel Invert (Address 17h) .............................................................................................. 50
6.12.1 Invert Signal Polarity (INV_AINX) ........................................................................................ 50
6.13 Status Control (Address 18h) ....................................................................................................... 51
6.13.1 Interrupt Pin Control (INT[1:0]) ............................................................................................ 51
6.14 Status (Address 19h) (Read Only) ............................................................................................... 51
6.14.1 DAC CLOCK ERROR (DAC_CLK ERROR) ....................................................................... 51
6.14.2 ADC CLOCK ERROR (ADC_CLK ERROR) ....................................................................... 51
6.14.3 ADC Overflow (ADCX_OVFL) ............................................................................................. 51
6.15 Status Mask (Address 1Ah) .......................................................................................................... 52
6.16 MUTEC Pin Control (Address 1Bh) .............................................................................................. 52
DS648F3
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