CS42448_07 Datasheet, PDF (31/64 Pages) Cirrus Logic – 108 dB, 192 kHz 6-In, 8-Out CODEC

CS42448
4.5 CODEC Digital Interface Formats
The ADC and DAC serial ports support the I²S, Left-Justified, Right-Justified, One-Line Mode (OLM) and
TDM digital interface formats with varying bit depths from 16 to 32 as shown in Figures 15-19. Data is
clocked out of the ADC on the falling edge of SCLK and clocked into the DAC on the rising edge. The serial
bit clock, DAC_SCLK and/or ADC_SCLK, must be synchronously derived from the master clock and be
equal to 256x, 128x, 64x, 48x or 32x Fs, depending on the interface format selected and desired speed
mode. One-Line Mode #1 and One-Line Mode #2 will operate in master or slave mode. Refer to Table 5 for
required clock ratios. The SCLK to sample rate (LRCK) ratios are shown in Tables 5 through 8.
Ratio
MCLK/LRCK
SCLK/LRCK (Slave Mode)
SCLK/LRCK (Master Mode)
I²S, Left-Justified, Right-Justified
SSM
256x, 384x, 512x,
768x, 1024x
32x, 48x, 64x
64x
DSM
128x, 192x, 256x, 384x,
512x
32x, 48x, 64x
64x
QSM
64x, 96x, 128x, 192x,
256x
32x, 48x, 64x
64x
Table 5. I²S, LJ, RJ Clock Ratios
MCLK/LRCK
SCLK/LRCK (Slave Mode)
SCLK/LRCK (Master Mode)
OLM #1
SSM
256x, 384x, 512x,
768x, 1024x
128x
128x
DSM
256x, 384x, 512x
128x
128x
Table 6. OLM#1 Clock Ratios
QSM
N/A
N/A
N/A
MCLK/LRCK
SCLK/LRCK (Slave Mode)
SCLK/LRCK (Master Mode)
OLM #2
SSM
256x, 384x, 512x,
768x, 1024x
256x
256x
DSM
256x, 384x, 512x
256x
256x
Table 7. OLM#2 Clock Ratios
QSM
N/A
N/A
N/A
MCLK/LRCK
SCLK/LRCK (Slave Mode)
SCLK/LRCK (Master Mode)
TDM
SSM
256x, 384x, 512x,
768x, 1024x
256X
N/A
DSM
256x, 384x, 512x
256X
N/A
Table 8. TDM Clock Ratios
QSM (DAC only)
256x
256X
N/A
DS648F3
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