CS42448_07 Datasheet, PDF (25/64 Pages) Cirrus Logic – 108 dB, 192 kHz 6-In, 8-Out CODEC

CS42448
The gain/attenuation of the signal can be adjusted for each AINx independently through the “AINX Volume
Control (Address 11h-16h)” on page 50.
The ADC output data is in 2’s complement binary format. For inputs above positive full scale or below neg-
ative full scale, the ADC will output 7FFFFFH or 800000H, respectively, and cause the ADC Overflow bit
in the register “Status (Address 19h) (Read Only)” on page 51 to be set to a ‘1’.
5.0 V
3.9 V
2.5 V
1.1 V
3.9 V
2.5 V
1.1 V
VA
AINx+
AINx-
Full-Scale Differential Input Level =
(AINx+) - (AINx-) = 5.6 VPP = 1.98 VRMS
Figure 10. Full-Scale Input
4.2.2
ADC3 Analog Input
ADC3 accommodates differential as well as single-ended inputs. In Single-Ended Mode, an internal MUX
selects from up to four single-ended inputs.
AIN5A
Single-Ended Input Filter
AIN5B
Single-Ended Input Filter
58
AIN5+/-
Differential
Input Filter
57
ADC3
AIN5_MUX
1
0
1
0
0
VQ ¹
AIN6_MUX
ADC3 SINGLE
+
AIN5
-
AIN6+/-
Differential
Input Filter
AIN6A _{Single-Ended Input Filter}
1
0
60
59
1
0
+
AIN6
-
0
VQ ¹
AIN6B _{Single-Ended Input Filter}
Figure 11. ADC3 Input Topology
DS648F3
25