CS4226 Datasheet, PDF (5/60 Pages) Cirrus Logic – Surround Sound Codec

CS4226
SWITCHING CHARACTERISTICS (T_A = 25°C; VA+, VD+ = +5V ±5%, outputs loaded with 30 pF)
Parameter
Symbol Min
Typ
Max
Units
Audio ADC's & DAC's Sample Rate
Fs
4
-
50
kHz
XTI Frequency
(XTI = 256, 384, or 512 Fs)
1.024
-
26
MHz
XTI Pulse Width High
XTI = 512 Fs
XTI = 384 Fs
XTI = 256 Fs
10
-
21
-
31
-
-
ns
-
ns
-
ns
XTI Pulse Width Low
XTI = 512 Fs
XTI = 384 Fs
XTI = 256 Fs
10
-
21
-
31
-
-
ns
-
ns
-
ns
PLL Clock Recovery Frequency RX, XTI, LRCK, LRCKAUX
30
-
50
kHz
XTI Jitter Tolerance
-
500
-
ps
PDN Low Time
(Note 9)
500
-
-
ns
SCLK Falling Edge to SDOUT Output Valid
(DSCK = 0) t_dpd
-
LRCK edge to MSB valid
t_lrpd
-
SDIN Setup Time Before SCLK Rising Edge
(DSCK=0) t_ds
-
SDIN Hold Time After SCLK Rising Edge
(DSCK=0) t_dh
-
Master Mode
-
(^{---3---8---41---})^{---F---s- + 20}
ns
-
40
ns
-
25
ns
-
25
ns
SCLK Period
SCLK Falling to LRCK Edge
SCLK Duty Cycle
t_sck
(^{---2---5---61---})^---F---s-
-
-
ns
(DSCK=0) t_mslr
-
±10
-
ns
-
50
-
%
Slave Mode
SCLK Period
SCLK High Time
SCLK Low Time
SCLK Rising to LRCK Edge
LRCK Edge to SCLK Rising
t_sckw
---------1----------
( 128 ) F s
-
t_sckh
40
-
t_sckl
40
-
(DSCK=0) t_lrckd
20
-
(DSCK=0) t_lrcks
40
-
-
ns
-
ns
-
ns
-
ns
-
ns
Notes: 9. After powering up the CS4226, PDN should be held low until the power supply is settled.
SCLK*
SCLKAUX*
(output)
LRCK
LRCKAUX
(output)
t _sck
t _mslr
SDOUT1
SDOUT2
Audio Ports Master Mode Timing
LRCK
LRCKAUX
(input)
t _lrckd
t _lrcks
t _sckh
tsckl
SCLK*
SCLKAUX*
(input)
SDIN1
SDIN2
SDIN3
DATAUX
SDOUT1
SDOUT2
t _sckw
t_{lrpd tds}
tdh
MSB
tdpd
MSB-1
*SCLK, SCLKAUX shown for DSCK = 0 and ASCK = 0.
SCLK & SCLKAUX inverted for DSCK = 1 and ASCK = 1, respectively.
Audio Ports Slave Mode and Data I/O timing
DS188F1
5