CS4226 Datasheet, PDF (18/60 Pages) Cirrus Logic – Surround Sound Codec

CS4226
Power-up/Reset/Power Down Mode
Upon power up, the user should hold PDN=0 until
the system’s power supply has stabilized. In this
state, the control port is reset to its default settings.
When PDN goes high, the device remains in a low
power mode in which the control port is active, but
CMOUT will not supply current. The desired set-
tings should be loaded in while keeping the RS bit
set to 1. Normal operation is achieved by setting the
RS bit to zero in the Converter Control Byte. Once
set to 0, the part powers up and an offset calibration
occurs. This process lasts approximately 50 ms.
Reset/power down is achieved by lowering the
PDN pin causing the part to enter power down.
Once PDN goes high, the control port is functional
and the desired settings should be loaded in while
keeping the RS bit set to 1. The remainder of the
chip remains in a low power reset state until the RS
bit in the Converter Control Byte is set to 0.
The CS4226 will also enter a stand-by mode if the
master clock source stops for approximately 10 µs
or if the LRCK is not synchronous to the master
clock. The control port will retain its current set-
tings when in stand-by mode.
DAC Calibration
Output offset voltage is minimized by an internal
calibration cycle. A calibration will automatically
occur anytime the part comes out of reset, includ-
ing the power-up reset, when the master clock
source to the part changes by changing the CS or CI
bits in the Clock Mode Byte or when the PLL goes
out of lock and then re-locks.
The CS4226 can be re-calibrated whenever de-
sired. A control bit, CAL, in the Converter Control
Byte, is provided to initiate a calibration. The se-
quence is:
1) Set CAL to 1, the CS4226 sets CALP to 1 and
begins to calibrate.
2) CALP will go to 0 when the calibration is com-
pleted.
Additional calibrations can be implemented by set-
ting CAL to 0 and then to 1.
De-Emphasis
The S/PDIF receiver can be enabled to process 24
bits of received data (20 bits of audio data and four
auxiliary bits) or process 20 bits of audio data (no
auxiliary bits). Setting DEM24=0 in the Auxiliary
Port Control Byte, will enable all 24 received data
bits to be processed with de-emphasis when de-em-
phasis is enabled. When setting DEM24=1, the
four auxiliary bits in the receiver data stream will
pass through unchanged and only the 20 audio data
bits will be processed.
The CS4226 is capable of digital de-emphasis for
32, 44.1, or 48 kHz sample rates. Implementation
of digital de-emphasis requires reconfiguration of
the digital filter to maintain the filter response
shown in Figure 9 at multiple sample rates. The
Auxiliary Port Control Byte selects the de-empha-
sis control method. De-emphasis may be enabled
under hardware control, using the DEM pin
(DEM2/1/0=4,5,6), by software control using the
DEM bit (DEM2/1/0=0,1,2,3), or by the emphasis
bits in the channel status data when the S/PDIF re-
ceiver is chosen as the clock source (DEM2/0/1=7).
If no frequency information is present, the filter de-
faults to 44.1 kHz.
Gain
dB
0dB
T1=50 µs
-10dB
T2 = 15 µs
F1
F2 Frequency
Figure 9. De-emphasis Curve
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