CS4226 Datasheet, PDF (39/60 Pages) Cirrus Logic – Surround Sound Codec

CDB4226
JUMPER
HDR5,
HDR6,
HDR7,
HDR8
XT_SEL
RX_SEL
CLK_SEL
PURPOSE
POSITION
Sets the direction of AIN3R/AUDIO, AIN
AIN3L/AUTODATA, AIN2L/FREQ0, and
AIN2R/FREQ1. All four jumpers must
be set to the same position, and corre- CSOUT
spond with the CSP bit in AUX Port
Control Byte.
Selects the configuration for the XT pin XTIN
on the DSP port. Jumper position must
correspond with the DMS1/0 bits in the XTAL
DSP Port Mode Byte and with the direc-
tion of the transceiver, U16.
XTOUT
Routes S/PDIF datastream from
RX2
RX_OPT to one of three S/PDIF
RX3
receiver input pins on the CS4226,
RX4
RX2, 3, or 4. Jumper position must cor- RX_AUXB
respond with the CS2/1/0 bits in the
Clock Mode Byte.
Tristates CLKOUT1 on AUX_HDR,
CLKOFF
allowing AUX_HDR to be compatible CLKOUT1
with 10-pin serial data connectors found
on other Crystal CDB capture boards.
FUNCTION SELECTED
Pins 9-12 on CS4226 are analog inputs
(CSP=0).
Pins 9-12 on CS4226 are channel status out-
puts (CSP=1).
XT is input to XTI. Y1 must be removed. U16
must be configured as input.
XT is disconnected from XTI/XTO and is
grounded through 47K resistor.
XT outputs XTO clock from CS4226. U16
must be configured as output.
Sends optical input to RX2 of CS4226.
Sends optical input to RX3 of CS4226.
Sends optical input to RX4 of CS4226.
Configures board for AUX port input.
Tristates CLKOUT1 buffer on U3.
Enables CLKOUT1 buffer on U3.
Table 1. Jumper-selectable Options
inputs AIN2R and AIN1R become differential in-
puts AINR- and AINR+, respectively. Selection of
the differential mode is made with the AIS1/0 bits
in the ADC Control Byte. The balanced input con-
figuration can be tested using special cables which
have a male XLR connector on one end and a pair
of RCA connectors on the other end.
ANALOG OUTPUTS
The six DAC outputs, AOUT1-AOUT6, are passed
through a 2-pole Butterworth low-pass filter and
are AC coupled, as shown in Figure 6 (-3 dB at
44.1 kHz). Each output will produce a nominal 1
Vrms output for a full scale digital input. Note that
the filter outputs, OUT1-OUT6, are noninverting.
The output filters in Figure 6 have additional resis-
tor and capacitor sockets to accomodate a 3-pole
Butterworth filter This may be useful if increased
out-of-band noise filtering is desired.
The CS4226 provides a common mode biasing
voltage of approximately 2.3 V on its CMOUT pin.
The CDB4226 analog inputs and outputs are AC
coupled, and hence CMOUT is not required on the
input and output filter stages. Since other filter to-
pologies may need a common mode bias voltage, a
buffered version of CMOUT is available on the test
point labeled CMOUTFO (Figure 4).
CLOCK CONFIGURATIONS
The timing on the board should be generated by a
single clock source, with the DSP port and AUX
port operating synchronously to the selected clock
source. Operating the serial audio interfaces at
clock frequencies which deviate from each other
will cause the CS4226 to reset its data paths in an
attempt to resynchronize. Potential clock sources
are:
1) the recovered clock from the S/PDIF receiver
on the CS4226,
DS188DB1
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