CS4226 Datasheet, PDF (15/60 Pages) Cirrus Logic – Surround Sound Codec

CS4226
and all ADC channels are combined onto a single
output. Format 6 is available in Master Mode only.
See figure 6 for details.
Auxiliary Audio Port Signals
The auxiliary port provides an alternate way to in-
put digital audio signals into the CS4226, and al-
lows the CS4226 to synchronize the system to an
external digital audio source. This port consists of
serial clock, data and left/right clock pins named,
SCLKAUX, DATAUX and LRCKAUX. The
Auxiliary Audio Port input is output on SDOUT1
when the IS bits are set to 1 or 2 in the ADC Control
Byte. Additionally, setting IS to 2 routes the stereo
ADC outputs to SDOUT2. There is approximately
a two frame delay from DATAUX to SDOUT1.
When the auxiliary port is used, the frequency of
LRCKAUX must equal to the system sample rate,
Fs, but no particular phase relationship is required.
De-emphasis and muting on error conditions can be
performed on input data to the auxiliary audio port;
this is controlled by the Auxiliary Port Control
Byte.
Auxiliary Audio Port Formats
Data input on DATAUX is clocked into the part by
SCLKAUX using the format selected in the Auxil-
iary Port Mode Byte. The auxiliary audio port sup-
ports the same 5 formats as the audio DSP port in
multi-data line mode. LRCKAUX is used to indi-
cate left and right data samples, and the start of a
new sample period. SCLKAUX and LRCKAUX
may be output from the CS4226, or they may be
generated from an external source, as set by the
AMS1/0 control bits in the Auxiliary Port Mode
Byte.
S/PDIF Receiver
The CS4226 reconfigures its auxiliary digital audio
port as an S/PDIF receiver if CS2/1/0 in the Clock
Mode Byte are set to be 4, 5, 6, or 7. In this mode
RX1, RX2, RX3, or RX4 can be chosen as the
S/PDIF input source.
The PLL will lock to the requested data source and
setting IS1/0 = 1 or 2 in the ADC Control Byte
routes the recovered output to SDOUT1 (channel A
to left, channel B to right). All 24 received data bits
will pass through the part to SDOUT1 except when
the serial port is configured with 32 SCLK’s per
frame or in Format 5. For these cases, the 16 or 20
MSB’s respectively will be output.
The error flags are reported in the Receiver Status
Byte. The LOCK bit indicates whether the PLL is
locked to the incoming S/PDIF data. Parity, Bi-
phase, or Validity errors (PAR=1, BIP=1 or V=1)
will cause the last valid data sample to be held at
the receiver input until the error condition no long-
er is present (see Hold section). Mute on extended
hold can also be enabled through the Auxiliary Port
Control Byte (see Hold section).
Other error flags include confidence, CONF, and
cyclic redundancy check, CRC. The CONF flag oc-
curs when the received data eye opening is less
than half a bit period. This indicates that the quality
of the transmission link is poor and does not meet
the digital audio interface standards. The CRC flag
is updated at the beginning of a channel status
block and is only valid when the professional for-
mat of channel status data is received. This error
indicates when the CS4226 calculated CRC value
does not match the CRC byte of the received chan-
nel status block.
The OVL/ERR pin will go high to flag an error. It
is a latched logical OR of the Parity, Biphase, Va-
lidity, and Lock error flags in the Receiver Status
Byte which is reset at the end of each frame. How-
ever, Parity, Biphase, or Validity errors can be
masked from the pin by clearing the PM, BM, and
VM bits respectively, of the Input Control Byte.
The first four bytes of the Channel Status block for
both channel A and B can be accessed in the Re-
ceiver Channel Status Bytes. When the CV bit is
DS188F1
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