CS4226 Datasheet, PDF (42/60 Pages) Cirrus Logic – Surround Sound Codec

CDB4226
DSP PORT
The DSP port header, DSP_HDR, provides access
to the DSP port of the CS4226. The eleven clock,
control, and data lines are defined in Table 2. The
XT, SCLK, and LRCK lines can be inputs or out-
puts, and their I/O configuration is defined in the
“Clock Configuration” section above. CLKOUT,
SDOUT1, and SDOUT2 are buffered outputs from
the CS4226. The serial data input lines, SDIN1, 2,
and 3, provide external access to the SDIN1, 2, and
3 pins of the CS4226. The I²C interface lines, la-
beled SDA/CDOUT1 and SCL/CCLK1, allow
configuration of the CS4226 registers without hav-
ing to use the PC connector, PC CONN.
The Altera EPM7032 programmable logic device
(PLD), shown in Figure 11, is used to route serial
audio data in several ways on the board. The
switches on S2 labeled SDIN_M2/M1/M0 (Figure
11) select the input to the SDIN1, 2 and 3 pins of
the CS4226. The various routing schemes are de-
fined in Table 3. There are seven loopback config-
urations which are selected by setting
SDIN_M2/M1/M0 to 0-6 (hex). To access the
SDIN pins on the codec from the DSP port header,
SDIN_M2/M1/M0 should be set to 7 (hex).
S/PDIF OUTPUT
A CS8402A digital audio transmitter, shown in
Figure 9, allows serial data from either SDOUT1 or
SDOUT2 to be transmitted in S/PDIF form through
an optical transmitter (8402_OPT) and through an
RCA connector (8402_DIG). The transmitter pro-
vides a convenient way to evaluate the perfor-
mance of the A/D converters on the CS4226.
The DIP switches SW1 and S2 (Figure 9) configure
the PLD to adjust the clock and data outputs of the
CS4226 to the format requirements of the
CS8402A. The functionality of each switch is de-
scribed below.
CS8402A MCLK Generation
The CLKOUT signal of the CS4226 can be 1 Fs,
256 Fs, 384 Fs, or 512 Fs. The CS8402A requires
a master clock frequency of 128 Fs to operate.
When CLKOUT is 1 Fs, the CS8402A will be in-
operable. However, to accomodate the other possi-
ble frequencies of CLKOUT, the evaluation board
can be configured to divide CLKOUT by 2, 3, or 4
to generate a 128 Fs master clock for the transmit-
ter. The switches on SW1 labeled MCLK_S1 and
MCLK_S0 select the degree of clock division as
defined in Table 3.
CS8402A Format Selection
The five switches on SW1 and S2 labeled
SP_RISING, SP_L_RB, BITS1, BITS0, and I2S
are used to select the correct digital interface for-
mat for the CS8402A. These switches are defined
in Table 3. Their settings must correspond with the
DSCK and DDF2/1/0 bits in the DSP Port Mode
Byte register. Table 4 shows which DSP Port
Mode Byte settings the CS8402A can support for
S/PDIF transmission. All other settings not listed
in the table are not valid.
SDOUTx Output Selection
The switch on S2 labeled SDOUT_M0 selects the
source of data to the CS8402A. A logic low selects
SDOUT1 for transmission, and a logic high selects
SDOUT2.
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