CS4226 Datasheet, PDF (25/60 Pages) Cirrus Logic – Surround Sound Codec

CS4226
DSP Port Mode Byte (0Eh)
B7
DCK1
B6
DCK0
B5
DMS1
B4
DMS0
B3
DSCK
B2
DDF2
B1
DDF1
DDF2-DDF0
Data format
0 - Right justified, 20-bit
1 - Right justified, 18-bit
2 - Right justified, 16-bit
3 - Left justified, 20-bit in / 24-bit out
4 - I²S compatible, 20-bit in / 24-bit out
5 - One Data Line Mode (Fig. 6)
6 - One Data Line (Master Mode only, Fig. 6)
7 - Not used
DSCK
Set the polarity of clocking data
0 - Data clocked in on rising edge of SCLK, out on falling edge of SCLK
1 - Data clocked in on falling edge of SCLK, out on rising edge of SCLK
DMS1-DMS0
Sets the mode of the port
0 - Slave
1 - Master Burst - SCLKs are gated 128 fs clocks
2 - Master Non-Burst - SCLKs are evenly distributed (No 48 fs SCLK)
3 - not used - default to Slave
DCK1-DCK0 *
Set number of bit clocks per Fs period
0 - 128
1 - 48 - Master Burst or Slave mode only
2 - 32 - All formats will default to 16 bits
3 - 64
This register defaults to 00h.
* DCK1-DCK0 are ignored in formats 5 and 6.
B0
DDF0
DS188F1
25