CS42888_07 Datasheet, PDF (49/61 Pages) Cirrus Logic – 108 dB, 192 kHz 4-In, 8-Out CODEC

6.12 ADC Channel Invert (Address 17h)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
6.12.1 Invert Signal Polarity (INV_AINX)
3
INV_AIN4
2
INV_AIN3
1
INV_AIN2
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
CS42888
0
INV_AIN1
6.13 Status Control (Address 18h)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
INT1
2
INT0
1
Reserved
0
Reserved
6.13.1 Interrupt Pin Control (INT[1:0])
Default = 00
00 - Active high; high output indicates interrupt condition has occurred
01 - Active low, low output indicates an interrupt condition has occurred
10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.
11 - Reserved
Function:
Determines how the Interrupt pin (INT) will indicate an interrupt condition.
For DAC and ADC clock errors, the INT pin is set to “Level Active Mode” and will become active during
the clock error. For the ADCx_OVFL error, the INT pin is set to Level Active Mode and will become active
during the overflow error.
6.14 Status (Address 19h) (Read Only)
7
Reserved
6
Reserved
5
Reserved
4
3
DAC_CLK Error ADC_CLK Error
2
Reserved
1
ADC2_OVFL
0
ADC1_OVFL
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0. Status bits that are masked off in the associated
mask register will always be “0” in this register.
6.14.1 DAC CLOCK ERROR (DAC_CLK ERROR)
Default = x
Function:
Indicates an invalid MCLK to DAC_LRCK ratio. This status flag is set to “Level Active Mode” and becomes
active during the error condition. See “System Clocking” on page 29 for valid clock ratios.
DS717F2
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