CS42888_07 Datasheet, PDF (43/61 Pages) Cirrus Logic – 108 dB, 192 kHz 4-In, 8-Out CODEC

CS42888
MFreq2
0
0
0
0
1
MFreq1
0
0
1
1
X
MFreq0
0
1
0
1
X
Description
1.0290 MHz to 12.8000 MHz
1.5360 MHz to 19.2000 MHz
2.0480 MHz to 25.6000 MHz
3.0720 MHz to 38.4000 MHz
4.0960 MHz to 51.2000 MHz
SSM
256
384
512
768
1024
Ratio (xFs)
DSM
N/A
N/A
256
384
512
Table 11. MCLK Frequency Settings for TDM & OLM Interface Formats
QSM
N/A
N/A
N/A
N/A
256
6.5 Interface Formats (Address 04h)
7
FREEZE
6
AUX_DIF
5
DAC_DIF2
4
DAC_DIF1
3
DAC_DIF0
2
ADC_DIF2
1
ADC_DIF1
0
ADC_DIF0
6.5.1
Freeze Controls (FREEZE)
Default = 0
Function:
This function will freeze the previous settings of, and allow modifications to be made to the channel mutes,
the DAC and ADC Volume Control/Channel Invert registers without the changes taking effect until the
FREEZE is disabled. To have multiple changes in these control port registers take effect simultaneously,
enable the FREEZE bit, make all register changes, then disable the FREEZE bit.
6.5.2
Auxiliary Digital Interface Format (AUX_DIF)
Default = 0
0 - Left Justified
1 - I²S
Function:
This bit selects the digital interface format used for the AUX Serial Port. The required relationship between
the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options
are detailed in Figures 22-23.
6.5.3
DAC Digital Interface Format (DAC_DIF[2:0])
Default = 110
Function:
These bits select the digital interface format used for the DAC Serial Port. The required relationship between
the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format; the options are
detailed in the section “CODEC Digital Interface Formats” on page 30.
Refer to Table 9, “Serial Audio Interface Channel Allocations,” on page 33.
DAC_DIF2
0
0
0
DAC_DIF1
0
0
1
DAC_DIF0
0
1
0
Description
Left Justified, up to 24-bit data
I²S, up to 24-bit data
Right Justified, 24-bit data
Table 12. DAC Digital Interface Formats
Format
0
1
2
Figure
Figure 15
Figure 14
Figure 16
DS717F2
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