CS42888_07 Datasheet, PDF (3/61 Pages) Cirrus Logic – 108 dB, 192 kHz 4-In, 8-Out CODEC

CS42888
5. REGISTER QUICK REFERENCE ........................................................................................................ 38
6. REGISTER DESCRIPTION .................................................................................................................. 40
6.1 Memory Address Pointer (MAP) ..................................................................................................... 40
6.1.1 Increment (INCR) .................................................................................................................. 40
6.1.2 Memory Address Pointer (MAP[6:0]) ..................................................................................... 40
6.2 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 40
6.2.1 Chip I.D. (CHIP_ID[3:0]) ........................................................................................................ 40
6.2.2 Chip Revision (REV_ID[3:0]) ................................................................................................. 40
6.3 Power Control (Address 02h) ......................................................................................................... 41
6.3.1 Power Down ADC Pairs (PDN_ADCX) ................................................................................. 41
6.3.2 Power Down DAC Pairs (PDN_DACX) ................................................................................. 41
6.3.3 Power Down (PDN) ............................................................................................................... 41
6.4 Functional Mode (Address 03h) ..................................................................................................... 42
6.4.1 DAC Functional Mode (DAC_FM[1:0]) .................................................................................. 42
6.4.2 ADC Functional Mode (ADC_FM[1:0]) .................................................................................. 42
6.4.3 MCLK Frequency (MFREQ[2:0]) ........................................................................................... 42
6.5 Interface Formats (Address 04h) .................................................................................................... 43
6.5.1 Freeze Controls (FREEZE) ................................................................................................... 43
6.5.2 Auxiliary Digital Interface Format (AUX_DIF) ........................................................................ 43
6.5.3 DAC Digital Interface Format (DAC_DIF[2:0]) ....................................................................... 43
6.5.4 ADC Digital Interface Format (ADC_DIF[2:0]) ....................................................................... 44
6.6 ADC Control & DAC De-Emphasis (Address 05h) ......................................................................... 44
6.6.1 ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE) .................................................. 44
6.6.2 DAC De-Emphasis Control (DAC_DEM) ............................................................................... 45
6.6.3 ADC1 Single-Ended Mode (ADC1 SINGLE) ......................................................................... 45
6.6.4 ADC2 Single-Ended Mode (ADC2 SINGLE) ......................................................................... 45
6.7 Transition Control (Address 06h) .................................................................................................... 45
6.7.1 Single Volume Control (DAC_SNGVOL, ADC_SNGVOL) .................................................... 45
6.7.2 Soft Ramp and Zero Cross Control (ADC_SZC[1:0], DAC_SZC[1:0]) .................................. 46
6.7.3 Auto-Mute (AMUTE) .............................................................................................................. 46
6.7.4 Mute ADC Serial Port (MUTE ADC_SP) ............................................................................... 47
6.8 DAC Channel Mute (Address 07h) ................................................................................................. 47
6.8.1 Independent Channel Mute (AOUTX_MUTE) ....................................................................... 47
6.9 AOUTX Volume Control (Addresses 08h- 0Fh) .......................................................................... 47
6.9.1 Volume Control (AOUTX_VOL[7:0]) ...................................................................................... 47
6.10 DAC Channel Invert (Address 10h) .............................................................................................. 48
6.10.1 Invert Signal Polarity (INV_AOUTX) .................................................................................... 48
6.11 AINX Volume Control (Address 11h-14h) ..................................................................................... 48
6.11.1 AINX Volume Control (AINX_VOL[7:0]) .............................................................................. 48
6.12 ADC Channel Invert (Address 17h) .............................................................................................. 49
6.12.1 Invert Signal Polarity (INV_AINX) ........................................................................................ 49
6.13 Status Control (Address 18h) ....................................................................................................... 49
6.13.1 Interrupt Pin Control (INT[1:0]) ............................................................................................ 49
6.14 Status (Address 19h) (Read Only) ............................................................................................... 49
6.14.1 DAC CLOCK ERROR (DAC_CLK ERROR) ....................................................................... 49
6.14.2 ADC CLOCK ERROR (ADC_CLK ERROR) ....................................................................... 50
6.14.3 ADC Overflow (ADCX_OVFL) ............................................................................................. 50
6.15 Status Mask (Address 1Ah) .......................................................................................................... 50
6.16 MUTEC Pin Control (Address 1Bh) .............................................................................................. 50
6.17 MUTEC Polarity Select (MCPOLARITY) ...................................................................................... 50
6.18 Mute Control Active (MUTEC ACTIVE) ........................................................................................ 50
7. EXTERNAL FILTERS ........................................................................................................................... 51
7.1 ADC Input Filter .............................................................................................................................. 51
7.1.1 Passive Input Filter ................................................................................................................ 52
DS717F2
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