CS42888_07 Datasheet, PDF (36/61 Pages) Cirrus Logic – 108 dB, 192 kHz 4-In, 8-Out CODEC

CS42888
4.8 Interrupts
The CS42888 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt
input pin on the host microcontroller. The INT pin may be configured as an active low or active high CMOS
driver or an open-drain driver. This last mode is used for active low, wired-OR hook-ups, with multiple pe-
ripherals connected to the microcontroller interrupt input pin.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. See “Status
(Address 19h) (Read Only)” on page 49. Each source may be masked off through mask register bits. In ad-
dition, each source may be set to rising edge, falling edge, or level sensitive. Combined with the option of
level sensitive or edge sensitive modes within the microcontroller, many different configurations are possi-
ble, depending on the needs of the system designer.
4.9 Recommended Power-Up Sequence
1. Hold RST low until the power supply and clocks are stable. In this state, the control port is reset to its
default settings and VQ will remain low.
2. Bring RST high. The device will initially be in a low power state with VQ low. All features will default as
described in the “Register Quick Reference” on page 38.
3. Perform a write operation to the Power Control register (“Power Control (Address 02h)” on page 41) to
set bit 0 to a ‘1’b. This will place the device in a power down state.
4. Load the desired register settings while keeping the PDN bit set to ‘1’b.
5. Mute all DACs. Muting the DACs suppresses any noise associated with the CODEC's first initialization
after power is applied.
6. Set the PDN bit in the power control register to ‘0’b. VQ will ramp to approximately VA/2 according to
the Popguard specification in section “Popguard” on page 27.
7. Following approximately 2000 LRCK cycles, the device is initialized and ready for normal operation.
8. After the CODEC is initialized, wait ~90 LRCK cycles (~1.9 ms @48 kHz) and then unmute the DACs.
9. Normal operation begins.
4.10 Reset and Power-Up
It is recommended that reset be activated if the analog or digital supplies drop below the recommended op-
erating condition to prevent power-glitch-related issues.
The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either
through the application of power or by setting the RST pin high. However, the voltage reference will take
much longer to reach a final value due to the presence of external capacitance on the ADC/DAC_FILT+
pins. A time delay of approximately 400 ms is required after applying power to the device or after exiting a
reset state. During this voltage reference ramp delay, all serial ports and DAC outputs will be automatically
muted.
4.11 Power Supply, Grounding, and PCB Layout
As with any high-resolution converter, the CS42888 requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized. Figure 2 shows the recommended power ar-
rangements, with VA connected to clean supplies. VD, which powers the digital circuitry, may be run from
the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite bead. In this
case, no additional devices should be powered from VD.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS42888 as pos-
sible. The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same
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