CS42888_07 Datasheet, PDF (18/61 Pages) Cirrus Logic – 108 dB, 192 kHz 4-In, 8-Out CODEC

SWITCHING SPECIFICATIONS - ADC/DAC PORT
(Inputs: Logic 0 = DGND, Logic 1 = VLS, ADC_SDOUT C_LOAD = 15 pF.)
Slave Mode
Parameters (Note 21)
Symbol
RST pin Low Pulse Width
(Note 17)
MCLK Frequency
MCLK Duty Cycle
(Note 18)
Input Sample Rate (LRCK)
LRCK Duty Cycle
Single-Speed Mode F_s
Double-Speed Mode (Note 19) F_s
Quad-Speed Mode (Note 20) F_s
SCLK Duty Cycle
SCLK High Time
t_sckh
SCLK Low Time
t_sckl
LRCK Rising Edge to SCLK Rising Edge
t_fss
t_lcks
SCLK Rising Edge to LRCK Falling Edge
t_fsh
SCLK Falling Edge to ADC_SDOUT Output Valid
t_dpd
DAC_SDIN Setup Time Before SCLK Rising Edge
t_ds
DAC_SDIN Hold Time After SCLK Rising Edge
t_dh
DAC_SDIN Hold Time After SCLK Rising Edge
t_dh1
ADC_SDOUT Hold Time After SCLK Rising Edge
t_dh2
ADC_SDOUT Valid Before SCLK Rising Edge
t_dval
Master Mode
Output Sample Rate (LRCK)
LRCK Duty Cycle
All Speed Modes F_s
SCLK Frequency
SCLK Duty Cycle
LRCK Edge to SCLK Rising Edge
t_lcks
SCLK Falling Edge to ADC_SDOUT Output Valid
t_dpd
DAC_SDIN Setup Time Before SCLK Rising Edge
t_ds
DAC_SDIN Hold Time After SCLK Rising Edge
t_dh1
Min
1
0.512
45
4
50
100
45
45
8
8
5
16
-
3
5
5
10
15
-
45
-
45
-
-
3
5
CS42888
Max
Units
-
ms
50
MHz
55
%
50
kHz
100
kHz
200
kHz
55
%
55
%
-
ns
-
ns
-
ns
-
ns
35
ns
-
ns
-
ns
-
ns
-
ns
-
ns
MCLK / 256
55
64 x Fs
55
5
35
-
-
kHz
%
MHz
%
ns
ns
ns
ns
LRCK
SCLK
DAC_SDINx
ADC_SDOUTx
t_lcks
t_sckh
t_sckl
t_ds
t_dpd
t_dh
MSB
MSB
MSB-1
MSB-1
LRCK
(input)
t_fss
SCLK
(input)
DAC_SDIN1
ADC_SDOUT1
t_fsh
t_sckh
t_sckl
MSB
t_ds
t_dh1
MSB
MSB-1
t_dh2
t_dval
MSB-1
Figure 4. Serial Audio Interface Slave Mode Timing
Figure 5. TDM Serial Audio Interface Timing
18
DS717F2