CS42888_07 Datasheet, PDF (33/61 Pages) Cirrus Logic – 108 dB, 192 kHz 4-In, 8-Out CODEC

CS42888
4.5.7 I/O Channel Allocation
Interface
Digital Input/Output Format
I²S, LJ, RJ
DAC_SDIN1
OLM
TDM
I²S, LJ, RJ
ADC_SDOUT1
OLM
TDM
Analog Output/Input Channel Allocation
from/to Digital I/O
AOUT 1,2
AOUT 1,2,3,4,5,6
AOUT 1,2,3,4,5,6,7,8
AIN 1,2
AIN 1,2,3,4
AIN 1,2,3,4 (2 additional channels from AUX_SDIN)
Table 9. Serial Audio Interface Channel Allocations
4.6 AUX Port Digital Interface Formats
These serial data lines are used when supporting the TDM Mode of operation with an external ADC or
S/PDIF receiver attached. The AUX serial port operates only as a clock master. The AUX_SCLK will operate
at 64xFs, where Fs is equal to the ADC sample rate (ADC_LRCK). If the AUX_SDIN signal is not being
used, it should be tied to AGND via a pull-down resistor.
The AUX port will operate in either the Left-Justified or I²S digital interface format with bit depths ranging
from 16 to 24 bits. Settings for the AUX port are made through the register “Interface Formats (Address
04h)” on page 43.
4.6.1 I²S
AUX_LRCK
AUX_SCLK
AUX_SDIN
MSB
Left Channel
Right Channel
LSB
MSB
LSB
AUX1
AUX2
Figure 20. AUX I²S Format
MSB
4.6.2 Left-Justified
AUX_LRCK
AUX_SCLK
AUX_SDIN
MSB
Left Channel
Right Channel
AUX1
LSB
MSB
AUX2
Figure 21. AUX Left-Justified Format
LSB
MSB
4.7 Control Port Description and Timing
The control port is used to access the registers allowing the CS42888 to be configured for the desired op-
erational modes and formats. The operation of the control port may be completely asynchronous with re-
spect to the audio sample rates. However, to avoid potential interference problems, the control port pins
should remain static if no operation is required.
The control port has two modes: SPI and I²C, with the CS42888 acting as a slave device. SPI Mode is se-
lected if there is a high-to-low transition on the AD0/CS pin, after the RST pin has been brought high. I²C
Mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently
selecting the desired AD0 bit address state.
DS717F2
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