CS4245_07 Datasheet, PDF (45/57 Pages) Cirrus Logic – 104 dB, 24-Bit, 192 kHz Stereo Audio CODEC

6.5.2
Master Clock 2 Frequency (Bits 2:0)
CS4245
Function:
These bits set the frequency of the supplied MCLK2 signal. See Table 12 for the appropriate settings.
MCLK2 Divider
÷1
÷ 1.5
÷2
÷3
÷4
Reserved
Reserved
MCLK2 Freq2 MCLK2 Freq1 MCLK2 Freq0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
x
Table 12. MCLK 2 Frequency
6.6 Signal Selection - Address 06h
7
Reserved
6
AOutSel1
5
AOutSel0
4
Reserved
3
Reserved
2
Reserved
1
LOOP
6.6.1 Auxiliary Output Source Select (Bits 6:5)
Function:
These bits are used to select the analog output source. Please refer to Table 13.
0
ASynch
6.6.2
6.6.3
AOutSel1
0
0
1
1
AOutSel0
0
1
0
1
Auxiliary Output Source
High Impedance
DAC Output
PGA Output
Reserved
Table 13. Auxiliary Output Source Selection
Digital Loopback (Bit 1)
Function:
When this bit is set, an internal digital loopback from the ADC to the DAC are enabled. Please refer to
“Internal Digital Loopback” on page 35.
Asynchronous Mode (Bit 0)
Function:
When this bit is set, the DAC and ADC may be operated at independent asynchronous sample rates de-
rived from MCLK1 and MCLK2. When this bit is cleared, the DAC and ADC must operate at synchronous
sample rates derived from MCLK1.
DS656F2
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