CS4245_07 Datasheet, PDF (34/57 Pages) Cirrus Logic – 104 dB, 24-Bit, 192 kHz Stereo Audio CODEC

CS4245
4.7 Output Transient Control
The CS4245 uses Popguard^® technology to minimize the effects of output transients during power-up and
power-down. This technique eliminates the audio transients commonly produced by single-ended, single-
supply converters when it is implemented with external DC-blocking capacitors connected in series with the
audio outputs. To make best use of this feature, it is necessary to understand its operation.
4.7.1 Power-Up
4.7.2
When the device is initially powered-up, the audio outputs AOUTA and AOUTB are clamped to VQ2,
which is initially low. After the PDN bit is released (set to ‘0’), the DAC outputs begin to ramp with VQ2
towards the nominal quiescent voltage. This ramp takes approximately 200 ms to complete. The gradual
voltage ramping allows time for the external DC-blocking capacitors to charge to VQ2, effectively blocking
the quiescent DC voltage. Audio output will begin after approximately 2000 sample periods.
Power-Down
4.7.3
To prevent audio transients at power-down, the DC-blocking capacitors must fully discharge before turn-
ing off the power. In order to do this, either the PDN bit should be set or the device should be reset about
250 ms before removing power. During this time, the voltage on VQ2 and the DAC outputs discharge
gradually to GND. If power is removed before this 250 ms time period has passed, a transient will occur
when the VA supply drops below that of VQ2. There is no minimum time for a power cycle; power may be
re-applied at any time.
Serial Interface Clock Changes
When changing the DAC clock ratio or sample rate, it is recommended that zero data (or near zero data)
be present on SDIN for at least 10 LRCK samples before the change is made. During the clocking change,
the DAC outputs will always be in a zero data state. If non-zero serial audio input is present at the time of
switching, a slight click or pop may be heard as the DAC output automatically goes to its zero data state.
4.8 Auxiliary Analog Output
The CS4245 includes an auxiliary analog output through the AUXOUT pins. These pins can be configured
to output the analog input to the ADC as selected with the input MUX and gained or attenuated with the
PGA, the analog output of the DAC, or alternatively they may be set to high-impedance. See “Section 6.6.1
“Auxiliary Output Source Select (Bits 6:5)” on page 45” for information on configuring the auxiliary analog
output.
The auxiliary analog output can source very little current. As current from the AUXOUT pins increases, dis-
tortion will increase. For this reason, a high input impedance buffer must be used on the AUXOUT pins to
achieve full performance. Refer to the table in “Auxiliary Output Analog Characteristics” on page 17 for ac-
ceptable loading conditions.
4.9 De-Emphasis Filter
The CS4245 includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter re-
sponse is shown in Figure 15. The frequency response of the de-emphasis curve scales proportionally with
changes in sample rate, Fs. Please see Section 6.3.4 “De-Emphasis Control (Bit 1)” on page 43 for de-em-
phasis control.
The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 μs pre-emphasis
equalization as a means of noise reduction.
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