CS4245_07 Datasheet, PDF (32/57 Pages) Cirrus Logic – 104 dB, 24-Bit, 192 kHz Stereo Audio CODEC

CS4245
derived from MCLK1. For more information on Synchronous and Asynchronous Modes, see “Synchro-
nous / Asynchronous Mode” on page 30.
For each serial port, the serial bit clock must be equal to 128x, 64x, 48x or 32x Fs, depending on the de-
sired speed mode. If operating in Asynchronous Mode, the serial bit clock SCLK1 must be synchronously
derived from MCLK1 and SCLK2 must be synchronously derived from MCLK2. If operating in Synchro-
nous Mode, SCLK1, and SCLK2 must be synchronously derived from MCLK1. Refer to Table 3 for re-
quired serial bit clock to Left/Right clock ratios.
SCLK/LRCK Ratio
Single-Speed
32x, 48x, 64x, 128x
Double-Speed
32x, 48x, 64x
Quad-Speed
32x, 48x, 64x
Table 3. Slave Mode Serial Bit Clock Ratios
4.3 High-Pass Filter and DC Offset Calibration
When using operational amplifiers in the input circuitry driving the CS4245, a small DC offset may be driven
into the A/D converter. The CS4245 includes a high-pass filter after the decimator to remove any DC offset
which could result in recording a DC level, possibly yielding clicks when switching between devices in a mul-
tichannel system.
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the HPFFreeze bit (See “ADC High-Pass Filter Freeze (Bit 1)” on page 44.) is set during normal op-
eration, the current value of the DC offset for the each channel is frozen and this DC offset will continue to
be subtracted from the conversion result. This feature makes it possible to perform a system DC offset cal-
ibration by:
1. Running the CS4245 with the high-pass filter enabled until the filter settles. See the ADC Digital Filter
Characteristics section for filter settling time.
2. Disabling the high-pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the
calibration point and the CS4245.
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