CS4245_07 Datasheet, PDF (44/57 Pages) Cirrus Logic – 104 dB, 24-Bit, 192 kHz Stereo Audio CODEC

6.4.2
6.4.3
6.4.4
6.4.5
ADC Digital Interface Format (Bit 4)
CS4245
Function:
The required relationship between LRCK1, SCLK1 and SDOUT is defined by the ADC Digital Interface
Format bit. The options are detailed in Table 10 and may be seen in Figure 7 and Figure 8.
ADC_DIF
0
1
Description
Left-Justified, up to 24-bit data (default)
I²S, up to 24-bit data
Format
0
1
Mute ADC (Bit 2)
Table 10. ADC Digital Interface Formats
Figure
7
8
Function:
When this bit is set, the serial audio output of the both ADC channels is muted.
ADC High-Pass Filter Freeze (Bit 1)
Function:
When this bit is set, the internal high-pass filter is disabled.The current DC offset value will be frozen and
continue to be subtracted from the conversion result. See “High-Pass Filter and DC Offset Calibration” on
page 32.
ADC Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for serial audio port 1. Setting this bit selects Master
Mode, while clearing this bit selects Slave Mode.
6.5 MCLK Frequency - Address 05h
7
Reserved
6
MCLK1
Freq2
5
MCLK1
Freq1
4
MCLK1
Freq0
6.5.1 Master Clock 1 Frequency (Bits 6:4)
3
Reserved
2
MCLK2
Freq2
1
MCLK2
Freq1
0
MCLK2
Freq0
Function:
Sets the frequency of the supplied MCLK1 signal. See Table 11 for the appropriate settings.
MCLK1 Divider
÷1
MCLK1 Freq2 MCLK1 Freq1 MCLK1 Freq0
0
0
0
÷ 1.5
0
0
1
÷2
0
1
0
÷3
0
1
1
÷4
1
0
0
Reserved
1
0
1
Reserved
1
1
x
Table 11. MCLK 1 Frequency
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DS656F2