CS2200-CP_09 Datasheet, PDF (3/26 Pages) Cirrus Logic – Fractional-N Frequency Synthesizer

CS2200-CP
8.7 Function Configuration 2 (Address 17h) ........................................................................................ 22
8.7.1 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 22
9. CALCULATING THE USER DEFINED RATIO .................................................................................... 23
9.1 12.20 Format .................................................................................................................................. 23
10. PACKAGE DIMENSIONS .................................................................................................................. 24
THERMAL CHARACTERISTICS ......................................................................................................... 24
11. ORDERING INFORMATION .............................................................................................................. 25
12. REFERENCES .................................................................................................................................... 25
13. REVISION HISTORY .......................................................................................................................... 26
LIST OF FIGURES
Figure 1. Typical Connection Diagram ........................................................................................................ 5
Figure 2. Control Port Timing - I²C Format .................................................................................................. 8
Figure 3. Control Port Timing - SPI Format (Write Only) ............................................................................ 9
Figure 4. Delta-Sigma Fractional-N Frequency Synthesizer ..................................................................... 10
Figure 5. Internal Timing Reference Clock Divider ................................................................................... 11
Figure 6. REF_CLK Frequency vs a Fixed CLK_OUT .............................................................................. 11
Figure 7. External Component Requirements for Crystal Circuit .............................................................. 12
Figure 8. Ratio Feature Summary ............................................................................................................. 14
Figure 9. PLL Clock Output Options ......................................................................................................... 14
Figure 10. Auxiliary Output Selection ........................................................................................................ 15
Figure 11. Control Port Timing in SPI Mode ............................................................................................. 17
Figure 12. Control Port Timing, I²C Write .................................................................................................. 17
Figure 13. Control Port Timing, I²C Aborted Write + Read ....................................................................... 17
LIST OF TABLES
Table 1. Ratio Modifier .............................................................................................................................. 13
Table 2. Example 12.20 R-Values ............................................................................................................ 23
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