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CS2200-CP_09 Datasheet, PDF (14/26 Pages) Cirrus Logic – Fractional-N Frequency Synthesizer
5.2.4
CS2200-CP
Ratio Configuration Summary
The RUD is the user defined ratio stored in the register space. R-Mod is applied if selected. The user de-
fined ratio, and ratio modifier make up the effective ratio REFF, the final calculation used to determine the
output to input clock ratio. The effective ratio is then corrected for the internal dividers. The conceptual
diagram in Figure 8 summarizes the features involved in the calculation of the ratio values used to gen-
erate the fractional-N value which controls the Frequency Synthesizer.
Timing Reference Clock
(XTI/REF_CLK)
Effective Ratio REFF
User Defined Ratio RUD
Ratio
Ratio Format
12.20
RModSel[2:0]
Ratio
Modifier
Divide
RefClkDiv[1:0]
RefClkDiv[1:0]
R Correction
SysClk
N
Frequency
Synthesizer
PLL Outpu
Figure 8. Ratio Feature Summary
Referenced Control
Register Location
Ratio......................................“Ratio (Address 06h - 09h)” on page 21
RModSel[2:0] ........................“R-Mod Selection (RModSel[2:0])” section on page 20
RefClkDiv[1:0] .......................“Reference Clock Input Divider (RefClkDiv[1:0])” on page 22
5.3 PLL Clock Output
The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer.
The driver can be set to high-impedance with the ClkOutDis bit.
The output from the PLL automatically drives a static low condition while the PLL is un-locked (when the
clock may be unreliable). This feature can be disabled by setting the ClkOutUnl bit, however the state
CLK_OUT may then be unreliable during an unlock condition.
ClkOutUnl
PLL Locked/Unlocked
0
0
2:1 Mux
1
0
2:1 Mux
ClkOutDis
PLL Clock Output
PLLClkOut
PLL Clock Output Pin
(CLK_OUT)
PLL Output
1
Figure 9. PLL Clock Output Options
Referenced Control
Register Location
ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 22
ClkOutDis ..............................“PLL Clock Output Disable (ClkOutDis)” on page 20
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