CS2200-CP_09 Datasheet, PDF (18/26 Pages) Cirrus Logic – Fractional-N Frequency Synthesizer

CS2200-CP
Send stop condition, aborting write.
Send start condition.
Send 100111x1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
6.3 Memory Address Pointer
The Memory Address Pointer (MAP) byte comes after the address byte and selects the register to be read
or written. Refer to the pseudocode above for implementation details.
6.3.1
Map Auto Increment
The device has MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is
set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP
will auto increment after each byte is read or written, allowing block reads or writes of successive regis-
ters.
7. REGISTER QUICK REFERENCE
This table shows the register and bit names with their associated default values.
EnDevCfg1 and EnDevCfg2 bits must be set to 1 for normal operation.
WARNING: All “Reserved” registers must maintain their default state to ensure proper functional operation.
Adr Name
01h Device ID
p 19
02h Device Ctrl
p 19
03h Device Cfg 1
p 20
05h Global Cfg
p 21
06h
- 32-Bit Ratio
09h
16h Funct Cfg 1
p 22
17h Funct Cfg 2
p 22
7
Device4
0
Unlock
x
RModSel2
0
Reserved
0
MSB
MSB-8
LSB+15
LSB+7
Reserved
0
Reserved
0
6
5
4
3
2
1
0
Device3 Device2 Device1 Device0 Revision2 Revision1 Revision0
0
0
0
0
x
x
x
Reserved Reserved Reserved Reserved Reserved AuxOutDis ClkOutDis
x
x
0
0
0
0
0
RModSel1 RModSel0 Reserved Reserved AuxOutSrc1 AuxOutSrc0 EnDevCfg1
0
0
0
0
0
0
0
Reserved Reserved Reserved Freeze Reserved Reserved EnDevCfg2
0
0
0
0
0
0
0
........................................................................................................................... MSB-7
........................................................................................................................... MSB-15
........................................................................................................................... LSB+8
...........................................................................................................................
LSB
AuxLockCfg Reserved RefClkDiv1 RefClkDiv0 Reserved Reserved Reserved
0
0
0
0
0
0
0
Reserved Reserved ClkOutUnl Reserved Reserved Reserved Reserved
0
0
0
0
0
0
0
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