CS2200-CP_09 Datasheet, PDF (16/26 Pages) Cirrus Logic – Fractional-N Frequency Synthesizer

thesizer. This includes all the bits shown in Figure 8 on page 14.
• Any discontinuities on the Timing Reference Clock, REF_CLK.
CS2200-CP
5.6 Required Power Up Sequencing
• Apply power to the device. The output pins will remain low until the device is configured with a valid ratio
via the control port.
• Write the desired operational configurations. The EnDevCfg1 and EnDevCfg2 bits must be set to 1 dur-
ing the initialization register writes; the order does not matter.
– The Freeze bit may be set prior to this step and cleared afterward to ensure all settings take effect
at the same time.
6. SPI / I²C CONTROL PORT
The control port is used to access the registers and allows the device to be configured for the desired operational
modes and formats. The operation of the control port may be completely asynchronous with respect to device inputs
and outputs. However, to avoid potential interference problems, the control port pins should remain static if no op-
eration is required.
The control port operates with either the SPI or I²C interface, with the CS2200 acting as a slave device. SPI Mode
is selected if there is a high-to-low transition on the AD0/CS pin after power-up. I²C Mode is selected by connecting
the AD0/CS pin through a resistor to VD or GND, thereby permanently selecting the desired AD0 bit address state.
In both modes the EnDevCfg1 and EnDevCfg2 bits must be set to 1 for normal operation.
WARNING: All “Reserved” registers must maintain their default state to ensure proper functional operation.
Referenced Control
Register Location
EnDevCfg1 ............................“Enable Device Configuration Registers 1 (EnDevCfg1)” on page 21
EnDevCfg2 ............................“Enable Device Configuration Registers 2 (EnDevCfg2)” section on page 21
6.1 SPI Control
In SPI Mode, CS is the chip select signal; CCLK is the control port bit clock (sourced from a microcontroller),
and CDIN is the input data line from the microcontroller. Data is clocked in on the rising edge of CCLK. The
device only supports write operations.
Figure 11 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The first
eight bits on CDIN form the chip address and must be 10011110. The next eight bits form the Memory Ad-
dress Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are
the data which will be placed into the register designated by the MAP.
There is MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the
MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will automatically incre-
ment after each byte is read or written, allowing block writes of successive registers.
6.2 I²C Control
In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the device by the clock, SCL.
There is no CS pin. The AD0 pin forms the least-significant bit of the chip address and should be connected
to VD or GND as appropriate. The state of the AD0 pin should be maintained throughout operation of the
device.
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