CS2200-CP_09 Datasheet, PDF (2/26 Pages) Cirrus Logic – Fractional-N Frequency Synthesizer

CS2200-CP
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 4
2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5
3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6
RECOMMENDED OPERATING CONDITIONS .................................................................................... 6
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6
DC ELECTRICAL CHARACTERISTICS ................................................................................................ 6
AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7
CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT ................................................... 8
CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT ................................................. 9
4. ARCHITECTURE OVERVIEW ............................................................................................................. 10
4.1 Delta-Sigma Fractional-N Frequency Synthesizer ......................................................................... 10
5. APPLICATIONS ................................................................................................................................... 11
5.1 Timing Reference Clock Input ........................................................................................................ 11
5.1.1 Internal Timing Reference Clock Divider ............................................................................... 11
5.1.2 Crystal Connections (XTI and XTO) ...................................................................................... 12
5.1.3 External Reference Clock (REF_CLK) .................................................................................. 12
5.2 Output to Input Frequency Ratio Configuration ............................................................................. 12
5.2.1 User Defined Ratio (RUD) ..................................................................................................... 12
5.2.2 Ratio Modifier (R-Mod) .......................................................................................................... 13
5.2.3 Effective Ratio (REFF) .......................................................................................................... 13
5.2.4 Ratio Configuration Summary ............................................................................................... 14
5.3 PLL Clock Output ........................................................................................................................... 14
5.4 Auxiliary Output .............................................................................................................................. 15
5.5 Clock Output Stability Considerations ............................................................................................ 15
5.5.1 Output Switching ................................................................................................................... 15
5.5.2 PLL Unlock Conditions .......................................................................................................... 15
5.6 Required Power Up Sequencing .................................................................................................... 16
6. SPI / I²C CONTROL PORT ................................................................................................................... 16
6.1 SPI Control ..................................................................................................................................... 16
6.2 I²C Control ...................................................................................................................................... 16
6.3 Memory Address Pointer ............................................................................................................... 18
6.3.1 Map Auto Increment .............................................................................................................. 18
7. REGISTER QUICK REFERENCE ........................................................................................................ 18
8. REGISTER DESCRIPTIONS ................................................................................................................ 19
8.1 Device I.D. and Revision (Address 01h) ....................................................................................... 19
8.1.1 Device Identification (Device[4:0]) - Read Only ..................................................................... 19
8.1.2 Device Revision (Revision[2:0]) - Read Only ........................................................................ 19
8.2 Device Control (Address 02h) ........................................................................................................ 19
8.2.1 Unlock Indicator (Unlock) - Read Only .................................................................................. 19
8.2.2 Auxiliary Output Disable (AuxOutDis) ................................................................................... 19
8.2.3 PLL Clock Output Disable (ClkOutDis) .................................................................................. 20
8.3 Device Configuration 1 (Address 03h) ........................................................................................... 20
8.3.1 R-Mod Selection (RModSel[2:0]) ........................................................................................... 20
8.3.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) ............................................................. 20
8.3.3 Enable Device Configuration Registers 1 (EnDevCfg1) ........................................................ 21
8.4 Global Configuration (Address 05h) ............................................................................................... 21
8.4.1 Device Configuration Freeze (Freeze) ................................................................................ 21
8.4.2 Enable Device Configuration Registers 2 (EnDevCfg2) ....................................................... 21
8.5 Ratio (Address 06h - 09h) .............................................................................................................. 21
8.6 Function Configuration 1 (Address 16h) ........................................................................................ 22
8.6.1 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 22
8.6.2 Reference Clock Input Divider (RefClkDiv[1:0]) .................................................................... 22
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