CS2200-CP_09 Datasheet, PDF (15/26 Pages) Cirrus Logic – Fractional-N Frequency Synthesizer

CS2200-CP
5.4 Auxiliary Output
The auxiliary output pin (AUX_OUT) can be mapped, as shown in Figure 10, to one of three signals: refer-
ence clock (RefClk), additional PLL clock output (CLK_OUT), or a PLL lock indicator (Lock). The mux is con-
trolled via the AuxOutSrc[1:0] bits. If AUX_OUT is set to Lock, the AuxLockCfg bit is then used to control
the output driver type and polarity of the LOCK signal (see section 8.6.1 on page 22). If AUX_OUT is set to
CLK_OUT the phase of the PLL Clock Output signal on AUX_OUT may differ from the CLK_OUT pin. The
driver for the pin can be set to high-impedance using the AuxOutDis bit.
AuxOutSrc[1:0]
Timing Reference Clock
(RefClk)
PLL Clock Output
(PLLClkOut)
PLL Lock/Unlock Indication
(Lock)
3:1 Mux
AuxOutDis
AuxLockCfg
Auxiliary Output Pin
(AUX_OUT)
Figure 10. Auxiliary Output Selection
Referenced Control
Register Location
AuxOutSrc[1:0]......................“Auxiliary Output Source Selection (AuxOutSrc[1:0])” on page 20
AuxOutDis .............................“Auxiliary Output Disable (AuxOutDis)” on page 19
AuxLockCfg...........................“AUX PLL Lock Output Configuration (AuxLockCfg)” section on page 22
5.5 Clock Output Stability Considerations
5.5.1
Output Switching
CS2200 is designed such that re-configuration of the clock routing functions do not result in a partial clock
period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or disabling an
output, changing the auxiliary output source between REF_CLK and CLK_OUT, and the automatic dis-
abling of the output(s) during unlock will not cause a runt or partial clock period.
The following exceptions/limitations exist:
• Enabling/disabling AUX_OUT when AuxOutSrc[1:0] = 11 (unlock indicator).
• Switching AuxOutSrc[1:0] to or from 11 (unlock indicator)
(Transitions between AuxOutSrc[1:0] = [00,10] will not produce a glitch).
• Changing the ClkOutUnl bit while the PLL is in operation.
When any of these exceptions occur, a partial clock period on the output may result.
5.5.2
PLL Unlock Conditions
Certain changes to the clock inputs and registers can cause the PLL to lose lock which will affect the pres-
ence the clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go un-
locked:
• Changes made to the registers which affect the Fraction-N value that is used by the Frequency Syn-
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