CDB53L21 Datasheet, PDF (3/33 Pages) Cirrus Logic – Evaluation Board for CS53L21

CDB53L21
LIST OF FIGURES
Figure 1.General Configuration Tab ............................................................................................................ 8
Figure 2.ADC Configuration Tab ................................................................................................................. 9
Figure 3.ADC Volume Controls Tab .......................................................................................................... 10
Figure 4.Mix Volume Controls Tab ............................................................................................................ 11
Figure 5.Register Maps Tab - CS53L21 ................................................................................................... 12
Figure 6.Routing 4 ..................................................................................................................................... 14
Figure 7.Routing 6 ..................................................................................................................................... 14
Figure 8.Routing 8 ..................................................................................................................................... 15
Figure 9.Routing 10 ................................................................................................................................... 15
Figure 10.0 dB FFT, Single-Speed Mode ................................................................................................. 17
Figure 11.0 dB FFT, Double-Speed Mode ................................................................................................ 17
Figure 12.-60 dB FFT, Single-Speed Mode .............................................................................................. 17
Figure 13.-60 dB FFT, Double-Speed Mode ............................................................................................. 17
Figure 14.No Input FFT, Single-Speed Mode ........................................................................................... 17
Figure 15.No Input FFT, Double-Speed Mode .......................................................................................... 17
Figure 16.THD+N vs. Frequency, Single-Speed Mode ............................................................................. 18
Figure 17.THD+N vs. Frequency, Double-Speed Mode ........................................................................... 18
Figure 18.THD+N vs. Amplitude, Single-Speed Mode .............................................................................. 18
Figure 19.THD+N vs. Amplitude, Double-Speed Mode ............................................................................ 18
Figure 20.Fade-to-Noise Linearity, Single-Speed Mode ........................................................................... 18
Figure 21.Fade-to-Noise Linearity, Double-Speed Mode .......................................................................... 18
Figure 22.Frequency Response, Single-Speed Mode .............................................................................. 19
Figure 23.Frequency Response, Double-Speed Mode ............................................................................. 19
Figure 24.Channel Crosstalk, Single-Speed Mode ................................................................................... 19
Figure 25.Channel Crosstalk, Double-Speed Mode .................................................................................. 19
Figure 26.Block Diagram ........................................................................................................................... 22
Figure 27.CS53L21 (Part of Schematic Sheet 1) ...................................................................................... 23
Figure 28.Analog I/O (Part of Schematic Sheet 1) .................................................................................... 24
Figure 29.S/PDIF I/O (Schematic Sheet 2) ............................................................................................... 25
Figure 30.FPGA (Schematic Sheet 3) ....................................................................................................... 26
Figure 31.Level Shifters & I/O Stake Header (Schematic Sheet 4) .......................................................... 27
Figure 32.Control Port I/O (Schematic Sheet 5) ....................................................................................... 28
Figure 33.Power (Schematic Sheet 6)lm .................................................................................................. 29
Figure 34.Silk Screen ................................................................................................................................ 30
Figure 35.Top-Side Layer ......................................................................................................................... 31
Figure 36.Bottom-Side Layer .................................................................................................................... 32
LIST OF TABLES
Table 1. MCLK and Clock/Data Routing Options ...................................................................................... 13
Table 2. CS53L21 H/W Mode Control ....................................................................................................... 16
Table 3. System Connections ................................................................................................................... 20
Table 4. Jumper Settings .......................................................................................................................... 21
DS700DB1
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