CDB53L21 Datasheet, PDF (1/33 Pages) Cirrus Logic – Evaluation Board for CS53L21

CDB53L21
Evaluation Board for CS53L21
Features
 Selectable Analog Inputs
– Stereo Line-Level RCA Jacks
– Stereo Microphone 1/8” Jacks
 Stereo Microphone Input Jacks
 8- to 96-kHz S/PDIF Output
– CS8406 Digital Audio Transmitter
 I/O Stake Headers
– External Control Port Accessibility
– External DSP Serial Audio I/O Accessibility
 Independent, Regulated Supplies
 1.8 V to 3.3 V Logic Interface
 Hardware Control
– 4 Pre-Defined Switch Settings
 FlexGUI S/W Control - Windows^® Compatible
– Pre-Defined & User-Configurable Scripts
 Layout and Grounding Recommendations
Description
The CDB53L21 evaluation board is an excellent means
for evaluating the CS53L21 ADC. Evaluation requires
an analog audio source, an analog/digital analyzer and
power supplies. Optionally, a Windows PC-compatible
computer may be used to evaluate the CS53L21 in Soft-
ware Mode.
System timing can be provided by the CS53L21 with
supplied master clock, or by using an I/O stake header
with a DSP connected.
RCA phono jacks are provided for the CS53L21 analog
inputs. 1/8” jacks are also available for microphone in-
puts. A digital data output is available from the CS8406
via RCA phono or optical connectors.
The Windows software provides a GUI to make config-
uration of the CDB53L21 easy. The software
communicates through the PC’s serial port or USB port
to configure the control port registers so that all features
of the CS53L21 can be evaluated. The evaluation board
may also be configured to accept external timing and
data signals for operation in a user application during
system development.
ORDERING INFORMATION
CDB53L21
Evaluation Board
Software Mode
Control Port
Reset
S/PDIF Output
(CS8406)
Hardware Mode
Switches
FPGA
I²C/SPI Header
MCLK
Reset
CS53L21
Analog Input
(Line or MIC)
MCLK
Oscillator
(socket)
Reset
Reset
Clocks/Data Header
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Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
MARCH '06
DS700DB1