CDB53L21 Datasheet, PDF (13/33 Pages) Cirrus Logic – Evaluation Board for CS53L21

CDB53L21
3. HARDWARE MODE CONTROL
The CDB may be configured without the use of a software control port through the use of two switches, “FPGA H/W
Control” and “CS53L21 H/W Control.” These switches are enabled in Hardware Mode only and ignored in Software
Mode. The CDB53L21 automatically enters Hardware Mode upon initial power up, or when exiting Software Mode,
by terminating the Cirrus FlexGUI software or by disconnecting the RS-232 serial cable or USB cable.
3.1 FPGA H/W Control
The “FPGA H/W Control” switch S3 sets up the CDB in 4 pre-defined routing topologies in Hardware Mode.
The tables and figures below describe each switch setting. The At-A-Glance Controls table provides a quick
reference for all presets.
At-A-Glance Controls
S[3:2]
S[1] (See Note 1.)
S[0]
00 - Reserved
01 - I/O Header MCLK / I/O Header clocks/data route through
FPGA
0 - CS53L21 Slave Routing 0 - No Loopback Routing
1 - CS53L21 Master Routing 1 - Reserved
10 - Oscillator MCLK / I/O Header clocks/data route through FPGA
11 - Reserved
Signal S[3:0]
Routing
General Description
Detailed Description
0
0000
1
0001
2
0010
3
0011
Reserved
Reserved
Reserved
Reserved
4
Figure 6
5
6
Figure 7
7
0100
0101
0110
0111
I/O MCLK
I/O Clocks/Data
Reserved
CS53L21 Clocks, I/O Data
Reserved
1) I/O masters MCLK. 2) I/O masters PCM clocks.
3) SDOUT to CS8406 and I/O Header
1) I/O masters MCLK. 2) CS53L21 masters PCM clocks.
3) SDOUT to CS8406 and I/O Header
8
Figure 8
1000
9
1001
10
Figure 9
1010
11
1011
12-15 Reserved
Oscillator MCLK
I/O Clocks/Data
Reserved
CS53L21 Clocks, I/O Data
Reserved
1) Oscillator masters MCLK. 2) I/O masters PCM clocks.
3) SDOUT to CS8406 and I/O Header
1) Oscillator masters MCLK. 2) CS53L21 masters PCM clocks.
3) SDOUT to CS8406 and I/O Header
Table 1. MCLK and Clock/Data Routing Options
Notes:
1. The S[1] setting affects FPGA signal routing only and is independent of the M/S setting of the “CS53L21
H/W Control” switch S5. These settings must be made manually by the user and have to be consistent.
DS700DB1
13