CDB53L21 Datasheet, PDF (16/33 Pages) Cirrus Logic – Evaluation Board for CS53L21

CDB53L21
3.2 CS53L21 H/W Control
The stand-alone “CS53L21 H/W Control” switch S5 controls the Hardware Mode options of the CS53L21.
A description of each switch is outlined in the following table. See the CS53L21 Data Sheet, Section 4.2
“Hardware M
ode” for further details on setting these switches.
Switch
M/S (Note 1.)
MCLKDIV2
I2S/LJ (Note 2.)
Position
LO
HI
LO
HI
LO
HI
Function
LRCK and SCLK are inputs to CS53L21.
LRCK and SCLK are outputs to CS53L21.
Internal MCLK to CS53L21 not divided.
Internal MCLK to CS53L21 divided by 2.
CS53L21 Interface Format: Left-Justified.
CS53L21 Interface Format: I²S.
Table 2. CS53L21 H/W Mode Control
Notes: 1. The M/S setting affects the CS53L21 only and is independent of S[1] setting in the “FPGA H/W Control”
switch S3. These settings must be made manually by the user and have to be consistent.
2. The I2S/LJ setting affects the CS53L21 only. The S/PDIF Transmitter input data format in HW Mode is
always LJ and is independent of this setting. If the user desires I2S format PCM SDOUT data, the I/O
Header will have to be used.
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DS700DB1