CS4351_05 Datasheet, PDF (24/37 Pages) Cirrus Logic – 192 kHz Stereo DAC with 2 Vrms Line Out

6. REGISTER DESCRIPTION
** All register access is R/W unless specified otherwise**
CS4351
6.1 Chip ID - Register 01h
7
PART4
1
6
PART3
1
5
PART2
1
4
PART1
1
3
PART0
1
2
REV2
-
1
REV1
-
0
REV0
-
Function:
This register is Read-Only. Bits 7 through 3 are the part number ID which is 11111b and the remaining Bits
(2 through 0) are for the chip revision (Rev. A = 000, Rev. B = 001, ...)
6.2 Mode Control 1 - Register 02h
7
Reserved
0
6
DIF2
0
5
DIF1
0
4
DIF0
0
3
DEM1
0
2
DEM0
0
1
FM1
0
0
FM0
0
6.2.1 Digital Interface Format (DIF2:0) Bits 6-4
Function:
These bits select the interface format for the serial audio input.
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in Figures 5 through 7.
DIF2 DIF1 DIF0
DESCRIPTION
Format FIGURE
0
0
0 Left Justified, up to 24-bit data
0
0
1 I²S, up to 24-bit data
0 (Default)
5
1
6
0
1
0 Right Justified, 16-bit data
2
7
0
1
1 Right Justified, 24-bit data
3
7
1
0
0 Right Justified, 20-bit data
4
7
1
0
1 Right Justified, 18-bit data
5
7
1
1
0 Reserved
1
1
1 Reserved
Table 7. Digital Interface Formats
6.2.2 De-Emphasis Control (DEM1:0) Bits 3-2.
Gain
dB
Default = 0
00 - No De-emphasis
01 - 44.1 kHz De-emphasis
0dB
10 - 48 kHz De-emphasis
11 - 32 kHz De-emphasis
Function:
-10dB
T1=50 µs
T2 = 15 µs
Selects the appropriate digital filter to maintain the stan-
dard 15 µs/50 µs digital de-emphasis filter response at
32, 44.1 or 48 kHz sample rates. (See Figure 11.)
Note: De-emphasis is only available in Single-Speed Mode
F1
3.183 kHz
F2 Frequency
10.61 kHz
Figure 11. De-Emphasis Curve
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DS566F1