CS4351_05 Datasheet, PDF (15/37 Pages) Cirrus Logic – 192 kHz Stereo DAC with 2 Vrms Line Out

4. APPLICATIONS
CS4351
4.1 Sample Rate Range/Operational Mode Detect
The device operates in one of three operational modes. The allowed sample rate range in each mode will
depend on whether the Auto-Detect Defeat bit is enabled/disabled.
4.1.1
Auto-Detect Enabled
The Auto-Detect feature is enabled by default. In this state, the CS4351 will auto-detect the correct mode
when the input sample rate (F_s), defined by the LRCK frequency, falls within one of the ranges illustrated
in Table 1. Sample rates outside the specified range for each mode are not supported.
Input Sample Rate (F_S)
4 kHz - 50 kHz
84 kHz - 100 kHz
170 kHz - 200 kHz
MODE
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Table 1. CS4351 Auto-Detect
4.1.2
Auto-Detect Disabled
The Auto-Detect feature can be defeated only by the format bits in the control port register 02h. In this
state, the CS4351 will not auto-detect the correct mode based on the input sample rate (F_s). The opera-
tional mode must then be set manually according to one of the ranges illustrated in Table 2. Please refer
to Section 6.2.3 for implementation details. Sample rates outside the specified range for each mode are
not supported. In stand-alone mode it is not possible to disable auto-detect of sample rates.
FM1
0
0
1
1
FM0
0
1
0
1
Input Sample Rate (F_S)
Auto speed mode detect
4 kHz - 50 kHz
50 kHz - 100 kHz
100 kHz - 200 kHz
Table 2. CS4351 Mode Select
MODE
Auto
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
4.2 System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks.
The left/right clock, defined also as the input sample rate (F_s), must be synchronously derived from the
MCLK according to specified ratios. The specified ratios of MCLK to LRCK, along with several standard au-
dio sample rates and the required MCLK frequency, are illustrated in Tables 3 through 5.
Refer to Section 4.3 for the required SCLK timing associated with the selected Digital Interface Format and
to the “Switching Specifications - Serial Audio Interface” section on page 10 for the maximum allowed clock
frequencies.
DS566F1
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