CS4351_05 Datasheet, PDF (16/37 Pages) Cirrus Logic – 192 kHz Stereo DAC with 2 Vrms Line Out

CS4351
Sample Rate
(kHz)
32
44.1
48
MCLK (MHz)
256x
8.1920
11.2896
12.2880
384x
12.2880
16.9344
18.4320
512x
16.3840
22.5792
24.5760
768x
24.5760
33.8688
36.8640
Table 3. Single-Speed Mode Standard Frequencies
1024x
32.7680
45.1584
49.1520
1152x
36.8640
Sample Rate
(kHz)
64
88.2
96
MCLK (MHz)
128x
8.1920
11.2896
12.2880
192x
12.2880
16.9344
18.4320
256x
16.3840
22.5792
24.5760
384x
24.5760
33.8688
36.8640
Table 4. Double-Speed Mode Standard Frequencies
512x
32.7680
45.1584
49.1520
Sample Rate
(kHz)
176.4
192
MCLK (MHz)
64x
11.2896
12.2880
96x
16.9344
18.4320
128x
22.5792
24.5760
192x
33.8688
36.8640
Table 5. Quad-Speed Mode Standard Frequencies
= Denotes clock modes which are NOT auto detected
256x
45.1584
49.1520
4.3 Digital Interface Format
The device will accept audio samples in 1 of 4 digital interface formats in Stand-Alone mode, as illustrated
in Table 6, and 1 of 6 formats in Control Port mode, as illustrated in Table 7.
4.3.1 Stand-Alone Mode
The desired format is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship
between the LRCK, SCLK and SDIN, see Figures 5 through 7. For all formats, SDIN is valid on the rising
edge of SCLK. Also, SCLK must have at least 32 cycles per LRCK period in format 2, and 48 cycles per
LRCK period in format 3.
DIF0
0
0
1
1
DIF1
DESCRIPTION
0 I²S, up to 24-bit Data
1 Left Justified, up to 24-bit Data
0 Right Justified, 24-bit Data
1 Right Justified, 16-bit Data
FORMAT
0
1
2
3
FIGURE
6
5
7
7
Table 6. Digital Interface Format - Stand-Alone Mode
4.3.2
Control Port Mode
The desired format is selected via the DIF2, DIF1 and DIF0 bits in the Mode Control 2 register (see section
Section 6.2.1). For an illustration of the required relationship between LRCK, SCLK and SDIN, see
Figures 5 through 7. For all formats, SDIN is valid on the rising edge of SCLK. Also, SCLK must have at
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DS566F1