CS4351_05 Datasheet, PDF (11/37 Pages) Cirrus Logic – 192 kHz Stereo DAC with 2 Vrms Line Out

Switching Characteristics - Control Port - I²C^® Format
(Inputs: Logic 0 = GND, Logic 1 = VL, C_L = 20 pF)
Parameter
Symbol
Min
SCL Clock Frequency
f_scl
-
RST Rising Edge to Start
t_irs
500
Bus Free Time Between Transmissions
t_buf
4.7
Start Condition Hold Time (prior to first clock pulse)
t_hdst
4.0
Clock Low time
t_low
4.7
Clock High Time
t_high
4.0
Setup Time for Repeated Start Condition
t_sust
4.7
SDA Hold Time from SCL Falling
(Note 7)
t_hdd
0
SDA Setup time to SCL Rising
t_sud
250
Rise Time of SCL and SDA
t_rc, t_rc
-
Fall Time SCL and SDA
t_fc, t_fc
-
Setup Time for Stop Condition
t_susp
4.7
Acknowledge Delay from SCL Falling
t_ack
300
Notes:
7. Data must be held for sufficient time to bridge the transition time, t_fc, of SCL.
CS4351
Max
100
-
-
-
-
-
-
-
-
1
300
-
1000
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
RST
t _irs
Stop
Start
SDA
t _buf
t _hdst
t _high
Repeated
S ta rt _{t rd}
t _hdst
Stop
t _fd
t _fc
t _susp
SCL
t
low
t
hdd
t _sud t _ack
t _sust
t _rc
Figure 2. Control Port Timing - I²C Format
DS566F1
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