CS4351_05 Datasheet, PDF (17/37 Pages) Cirrus Logic – 192 kHz Stereo DAC with 2 Vrms Line Out

CS4351
least 32 cycles per LRCK period in format 2, 48 cycles in format 3, 40 cycles in format 4, and 36 cycles
in format 5.
LRCK
SCLK
SDIN
Left Channel
Right Channel
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 5. Left-Justified up to 24-Bit Data
LRCK
SCLK
SDIN
Left Channel
Right Channel
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 6. I²S, up to 24-Bit Data
LRCK
SCLK
SDIN MSB
Left Channel
Right Channel
MSB +1 +2 +3 +4 +5
-7 -6 -5 -4 -3 -2 -1 LSB
MSB +1 +2 +3 +4 +5
Figure 7. Right-Justified Data
-7 -6 -5 -4 -3 -2 -1 LSB
4.4 De-Emphasis Control
The device includes on-chip digital de-emphasis. Figure 8 shows the de-emphasis curve for F_s equal to 44.1
kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample
rate, Fs.
Gain
dB
T1=50 µs
0dB
-10dB
T2 = 15 µs
F1
3.183 kHz
F2 Frequency
10.61 kHz
Figure 8. De-Emphasis Curve
Note: De-emphasis is only available in Single-Speed Mode.
DS566F1
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