CS4351_05 Datasheet, PDF(21/37 Page) Cirrus Logic – 192 kHz Stereo DAC with 2 Vrms Line Out

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CS4351_05 Datasheet, PDF (21/37 Pages) Cirrus Logic – 192 kHz Stereo DAC with 2 Vrms Line Out

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CS4351

4.9.2.2 IÂ²C Read

To read from the device, follow the procedure below while adhering to the control port Switching Specifica-

tions.

1. Initiate a START condition to the IÂ²C bus followed by the address byte. The upper 6 bits must be

100110. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth

bit of the address byte is the R/W bit.

2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register

pointed to by the MAP. The MAP register will contain the address of the last register written to the

MAP, or the default address (see Section 4.10.2) if an IÂ²C read is the first operation performed on

the device.

3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.

4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers.

Continue providing a clock and issue an ACK after each byte until all the desired registers are read,

then initiate a STOP condition to the bus.

5. If the INCR bit is set to 0 and further IÂ²C reads from other registers are desired, it is necessary to

initiate a repeated START condition and follow the procedure detailed from steps 1 and 2 from the

IÂ²C Write instructions followed by step 1 of the IÂ²C Read section. If no further reads from other reg-

isters are desired, initiate a STOP condition to the bus.

SDA

100110

AD0

R/W ACK

NOTE

DATA

1-8

ACK

DATA

1-8

ACK

SCL

S ta rt

Stop

NOTE: If operation is a write, this byte contains the Memory Address Pointer, MAP. If

operation is a read, this byte contains the data of the register pointed to by the MAP.

Figure 9. Control Port Timing, IÂ²C Mode

4.9.3

SPI Mode

In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK

(see Figure 10 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and

is used to control SPI writes to the control port. When the device detects a high to low transition on the

AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs and data is clocked in on the

rising edge of CCLK.

4.9.3.1 SPI Write

To write to the device, follow the procedure below while adhering to the control port Switching Specifica-

tions in Section 8.

1. Bring CS low.

2. The address byte on the CDIN pin must then be 10011000.

3. Write to the memory address pointer, MAP. This byte points to the register to be written.

DS566F1

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