CS4351_05 Datasheet, PDF (22/37 Pages) Cirrus Logic – 192 kHz Stereo DAC with 2 Vrms Line Out

CS4351
4. Write the desired data to the register pointed to by the MAP.
5. If the INCR bit (see Section 4.9.1) is set to 1, repeat the previous step until all the desired registers
are written, then bring CS high.
6. If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring
CS high, and follow the procedure detailed from step 1. If no further writes to other registers are de-
sired, bring CS high.
)
CS
CCLK
CDIN
CHIP
ADDRESS
1001100
MAP
DATA
R/W
MSB
LSB
byte 1
byte n
MAP = Memory Address Pointer
Figure 10. Control Port Timing, SPI mode
4.10 Memory Address Pointer (MAP)
7
INCR
0
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
MAP3
0
4.10.1 INCR (AUTO MAP INCREMENT ENABLE)
Default = ‘0’
0 - Disabled
1 - Enabled
4.10.2 MAP (MEMORY ADDRESS POINTER)
Default = ‘0000’
2
MAP2
0
1
MAP1
0
0
MAP0
0
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DS566F1