THC63LVD1024_16 Datasheet, PDF (6/23 Pages) California Eastern Labs – 135MHz 67Bits LVDS Receiver

THC63LVD1024_Rev.3.02_E
Pin Description (Continued)
/PDWN
L
L
H
H
Table 1. Output Control
OE
Data Outputs
(Rxn)
L
Hi-Z
H
All Low
L
Hi-Z
H
Data Out
CLKOUT
Hi-Z
Fixed Low
Hi-Z
CLK Out
Absolute Maximum Ratings
Supply Voltage (V_CC)
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
LVDS Receiver Input Voltage
Output Current
Junction Temperature
Storage Temperature Range
Reflow Peak Temperature / Time
Maximum Power Dissipation @+25 C
-0.3V ~ +4.0V
-0.3V ~ (V_CC + 0.3V)
-0.3V ~ (V_CC + 0.3V)
-0.3V ~ (V_CC + 0.3V)
-30mA ~ 30mA
+125 C
-55 C ~ +125 C
+260 C / 10sec.
4.4W
Recommended Operating Conditions
Parameter
Min.
Typ
Max
Unit
All Supply Voltage
3.0
3.3
3.6
V
Operating Ambient Temperature
-40
-
85
C
MODE<1:0>=LL
Dual-in/Dual-out
LVDS Input
8
-
135
(80)*
MHz
Ta 70 C
(Ta 85 C )*
Output
8
-
135
(80)*
MHz
Single Edge Output LVDS Input
20
CLK
MODE<1:0>=LH
(MODE2=L)
Output
40
Frequency _{Dual-in/Single-out Double Edge Output LVDS Input}
20
(MODE2=H)
Output
20
-
75
MHz
-
150
MHz
-
75
MHz
-
75
MHz
MODE<1:0>=HL
Single-in/Dual-out
MODE<1:0>=HH
Single-in/Single-out
LVDS Input
8
Output
4
LVDS Input
8
Output
8
-
135
MHz
-
67.5 MHz
-
135
MHz
-
135
MHz
Copyright©2015 THine Electronics, Inc.
5/23
Security E
THine Electronics, Inc.