THC63LVD1024_16 Datasheet, PDF (11/23 Pages) California Eastern Labs – 135MHz 67Bits LVDS Receiver

THC63LVD1024_Rev.3.02_E
AC Timing Diagrams
TTL Output
80%
80%
20%
20%
TTL Output Load
t_TLH
t_THL
Fig3. CMOS/TTL Output Load and Transition Time
t_RCP
t_RCH
t_RCL
CLKOUT
V_CC/2
V_CC/2
V_CC/2
Fig4. CLKOUT Period and High/Low Time
V_CC/2
CLKOUT
V_CC/2
t_RCP
V_CC/2
V_CC/2
R/F=L
R/F=H
Rxn, Gxn, Bxn
xn == 10,~29
HSYNC,VSYNC
DE
CONT11,12
CONT21,22
V_CC/2
6 -t-D-----O2----8-U-----T--
7 ^{t--D-----O2----8-U-----T--}
V_CC/2
t_RS
V_CC/2
6 ^{t--D-----O2----8-U-----T--}
7 ^{t--D-----O2----8-U-----T--}
t_RH
V_CC/2
t_DOUT
Fig5. CLKOUT Position and Setup/Hold Timing
R/F=H
R/F=L
R/F=L
R/F=H
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