THC63LVD1024_16 Datasheet, PDF (4/23 Pages) California Eastern Labs – 135MHz 67Bits LVDS Receiver

THC63LVD1024_Rev.3.02_E
Pin Description
Pin Name
RA1+, RA1-
RB1+, RB1-
RC1+, RC1-
RD1+, RD1-
RE1+, RE1-
RCLK+, RCLK-
RA2+, RA2-
RB2+, RB2-
RC2+, RC2-
RD2+, RD2-
RE2+, RE2-
R19 ~ R10
G19 ~ G10
B19 ~ B10
R29 ~ R20
G29 ~ G20
B29 ~ B20
CONT11,CONT12
CONT21,CONT22
DE
VSYNC
HSYNC
CLKOUT
/PDWN
MODE1, MODE0
Pin #
111, 110
113, 112
117, 116
123, 122
125, 124
119, 118
129, 128
131, 130
135, 134
141, 140
143, 142
74 - 72, 69 - 63
86 - 82, 79 - 75
100, 99,
96-90, 87
25-23, 20-14
40, 37 - 31,
27, 26
52 - 48, 45 - 41
104, 105
55, 56
103
102
101
60
4
6, 5
Type
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
Description
The 1st Link. The 1st pixel input data when Dual Link.
LVDS Clock Input.
The 2nd Link. These pins are disabled when Single Link.
The 1st Pixel Data Outputs.
The 2nd Pixel Data Outputs.
User defined data output
Data Enable Output.
Vsync Output.
Hsync Output.
Clock Output.
Power down and Output Control.(Table1)
H: Normal operation
L: Power down
Pixel Data Mode.
MODE1 MODE0
H
H
H
L
L
H
L
L
Mode
Single Link (Single-in/Single-out)
Single Link (Single-in/Dual-out)
Dual Link (Dual-in/Single-out)
Dual Link (Dual-in/Dual-out)
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