THC63LVD1024_16 Datasheet, PDF (12/23 Pages) California Eastern Labs – 135MHz 67Bits LVDS Receiver

THC63LVD1024_Rev.3.02_E
AC Timing Diagrams (Continued)
t_RCP
CLKOUT
V_CC/2
V_CC/2
V_CC/2
V_CC/2
V_CC/2
7 ^{t--D-----O2----8-U-----T--}
V_CC/2
V_CC/2
7 ^{t--D-----O2----8-U-----T--}
V_CC/2
7 -t-D-----O2----8-U-----T--
7 ^{t--D-----O2----8-U-----T--}
R/F=L
R/F=H
R/F=L
R/F=H
R/F=L
R/F=H
R1n, G1n, B1n
t_RS
t_RH
t_RS
t_RH
n = 0~9
HSYNC,VSYNC
DE
V_CC/2
1st Pixel
Data
V_CC/2
2nd Pixel
Data
V_CC/2
CONT11,12
t_DOUT
t_DOUT
Fig6. CLKOUT Position and Setup/Hold Timing for Double Edge Output Mode
MODE<1:0>=LH, MODE2=H
RCLK
(Differential)
RCLK=(RCLK+)-(RCLK-)
V_diff = 0V
t_RCIH
t_RCIP
t_RCIL
V_diff = 0V
V_diff = 0V
Ryx+/-
x=1,2
y= A, B, C, D, E
Ryx3’ Ryx2’ Ryx1’ Ryx0’ Ryx6 Ryx5 Ryx4 Ryx3 Ryx2 Ryx1 Ryx0 Ryx6’’
Previous Cycle
t_RIP1
t_RIP0
t_RIP6
t_RIP5
t_RIP4
t_RIP3
t_RIP2
Current Cycle
Next Cycle
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Fig7. LVDS Input Data Position
11/23
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