THC63LVD1024_16 Datasheet, PDF (13/23 Pages) California Eastern Labs – 135MHz 67Bits LVDS Receiver

THC63LVD1024_Rev.3.02_E
AC Timing Diagrams (Continued)
RCLK+/-
/PDWN
CLKOUT
2.0V
t_RPLL
V_CC/2
Fig8. PLL Lock Loop Set Time
RCLK+
Ryx+/-
x=1,2
y= A, B, C, D, E
CLKOUT
R/F=L
R1n, G1n, B1n
n = 0~9
HSYNC,VSYNC
DE
CONT11,12
V_diff = 0V
Current Data
t_RCD
Note:
1) Vdiff = (RCLK+) - (RCLK-)
V_CC/2
Current Data
Fig9. RCLK +/- to CLKOUT Delay
RCLK+
DE
RC1+
DE
DE
DE
DE
DE
t_DEH
t_DEL
t_DEINT
Fig9-1. Single IN / Dual OUT mode RC1(DE) input timing
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