CS4265 Datasheet, PDF (39/53 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Stereo Audio CODEC

CS4265
6.12.1 DAC Soft Ramp or Zero Cross Enable (Bits 7:6)
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock
periods. See Table 15 on page 39.
Zero Cross Enable
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur
after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel. See Table 15 on page 39.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or
muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level
change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms
at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is
independently monitored and implemented for each channel. See Table 15 on page 39.
Table 15. DAC Soft Cross or Zero Cross Mode Selection
DACSoft
0
0
1
1
DACZeroCross
0
1
0
1
Mode
Changes to affect immediately
Zero Cross enabled
Soft Ramp enabled
Soft Ramp and Zero Cross enabled (default)
6.12.2 Invert DAC Output (Bit 5)
Function:
When this bit is set, the output of the DAC will be inverted.
6.13 Status - Address 0Dh
7
Reserved
6
Reserved
5
Reserved
4
EFTC
3
ClkErr
2
Reserved
1
ADCOvfl
0
ADCUndrfl
For all bits in this register, a ‘1’ means the associated condition has occurred at least once since the
register was last read. A ‘0’ means the associated condition has NOT occurred since the last reading
of the register. Status bits that are masked off in the associated mask register will always be ‘0’ in this
register. This register defaults to 00h.
6.13.1 E to F C-buffer Transfer
Function:
Indicates the completion of an E to F C-buffer transfer. See “Channel Status Buffer Management” on
page 50 for more information.
DS657A2
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