CS4265 Datasheet, PDF (30/53 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Stereo Audio CODEC

CS4265
It is recommended that RESET be activated if the analog or digital supplies drop below the recommended operating
condition to prevent power glitch related issues.
4.16 Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure
synchronous sampling, the master clocks and left/right clocks must be the same for all of the CS4265’s in the sys-
tem. If only one master clock source is needed, one solution is to place one CS4265 in Master Mode, and slave all
of the other CS4265’s to the one master. If multiple master clock sources are needed, a possible solution would be
to supply all clocks from the same external source and time the CS4265 reset with the inactive edge of master clock.
This will ensure that all converters begin sampling on the same clock edge.
4.17 Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4265 requires careful attention to power supply and grounding arrange-
ments if its potential performance is to be realized. Figure 9 shows the recommended power arrangements, with VA
connected to a clean supply. VD, which powers the digital filter, may be run from the system logic supply (VLS or
VLC) or may be powered from the analog supply (VA) via a resistor. In this case, no additional devices should be
powered from VD. Power supply decoupling capacitors should be as near to the CS4265 as possible, with the low
value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+ and
VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, partic-
ularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ and AGND. The CS4265 evaluation
board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the
CS4265 digital outputs only to CMOS inputs.
4.18 Package Considerations
The CS4265 is available in the compact QFN package. The under side of the QFN package reveals a large metal
pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally
dimensioned copper pad on the PCB and must be electrically connected to ground. A series of vias should be used
to connect this copper pad to one or more larger ground planes on other PCB layers. In split ground systems, it is
recommended that this thermal pad be connected to AGND for best performance. The CS4265 evaluation board
demonstrates the optimum thermal pad and via configuration.
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DS657A2