CS4265 Datasheet, PDF (25/53 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Stereo Audio CODEC

CS4265
functionality is not required, simply connect the SGND pin to AGND through the parallel combination of a 10 µF and
a 0.1 µF capacitor.
CS4265
AINA
-
VA
+
SGND
10 µF
In to PGA
0.1 µF
+
AINB
-
In to PGA
Note: If pseudo-differential input functionality is not required, the
connections shown with dashed line should be added.
Figure 12. Pseudo-Differential Input Stage
4.6 Output Connections
The CS4265 DAC’s implement a switched-capacitor filter followed by a continuous time low pass filter. Its response,
combined with that of the digital interpolator, is shown in the “DAC Filter Plots” section beginning on page 45. The
recommended external analog circuitry is shown in the Typical Connection Diagram.
The CS4265 DAC is a linear phase design and does not include phase or amplitude compensation for an external
filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry.
4.7 Output Transient Control
The CS4265 uses Popguard^™ technology to minimize the effects of output transients during power-up and power-
down. This technique eliminates the audio transients commonly produced by single-ended single-supply converters
when it is implemented with external DC-blocking capacitors connected in series with the audio outputs. To make
best use of this feature, it is necessary to understand its operation.
4.7.1 Power-up
When the device is initially powered-up, the DAC outputs AOUTA and AOUTB are clamped to VQ which is initially
low. After the PDN bit is released (set to ‘0’), the outputs begin to ramp with VQ towards the nominal quiescent volt-
age. This ramp takes approximately 200 ms to complete. The gradual voltage ramping allows time for the external
DC-blocking capacitors to charge to VQ, effectively blocking the quiescent DC voltage. Audio output will begin after
approximately 2000 sample periods.
4.7.2 Power-down
To prevent audio transients at power-down the DC-blocking capacitors must fully discharge before turning off the
power. In order to do this, either the PDN should be set or the device should be reset about 250 ms before removing
power. During this time, the voltage on VQ and the DAC outputs will gradually discharge to GND. If power is removed
before this 250 ms time period has passed a transient will occur when the VA supply drops below that of VQ. There
is no minimum time for a power cycle, power may be re-applied at any time.
4.7.3 Serial Interface Clock Changes
When changing the clock ratio or sample rate it is recommended that zero data (or near zero data) be present on
the selected SDIN pin for at least 10 LRCK samples before the change is made. During the clocking change the
DAC outputs will always be in a zero data state. If non-zero serial audio input is present at the time of switching, a
slight click or pop may be heard as the DAC output automatically goes to it’s zero data state.
DS657A2
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