CS4265 Datasheet, PDF (29/53 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Stereo Audio CODEC

CS4265
SCL
SDA
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
CHIP ADDRESS (WRITE)
1
START
00
1 1 1 AD0 0
INCR 6
ACK
MAP BYTE
STOP
CHIP ADDRESS (READ)
DATA
DATA +1
5 4 3210
1 0 0 1 1 1 AD0 1
70
70
ACK
ACK
ACK
START
DATA + n
70
NO
ACK _STOP
Figure 16. Control Port Timing, I²C Read
Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As shown in
Figure 16, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The
following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 100111x0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 100111x1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
4.14 Status Reporting
The CS4265 has comprehensive status reporting capabilities. Many conditions can be reported in the status regis-
ter, as listed in the status register descriptions. See “Status - Address 0Dh” on page 39. Each source may be masked
off through mask register bits. In addition, each source may be set to rising edge, falling edge, or level sensitive.
Combined with the option of level sensitive or edge sensitive modes within the microcontroller, many different con-
figurations are possible, depending on the needs of the equipment designer.
4.15 Reset
When RESET is low, the CS4265 enters a low power mode and all internal states are reset, including the control
port and registers, and the outputs are muted. When RESET is high, the control port becomes operational and the
desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the Power Control register
will then cause the part to leave the low power state and begin operation.
The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either through
the application of power or by setting the RESET pin high. However, the voltage reference will take much longer to
reach a final value due to the presence of external capacitance on the FILT+ pin. During this voltage reference ramp
delay, both SDOUT and DAC outputs will be automatically muted.
DS657A2
29