CS4265 Datasheet, PDF (28/53 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Stereo Audio CODEC

CS4265
rate information. In this “mono mode”, two cables are needed for stereo data transfer. The CS4265 offers mono
mode operation. The CS4265 is set placed into and out of mono mode with the MMT control bit.
In mono mode, the input port will run at the audio sample rate (Fs), while the IEC60958-3 transmitter frame rate will
be at Fs/2. Consecutive left or right channel serial audio data samples may be selected for transmission on the A
and B sub-frames, and the channel status block transmitted is also selectable.
Using mono mode is only necessary if the incoming audio sample rate is already at 192 kHz and contains both left
and right audio data words. The “mono mode” IEC60958-3 output stream may also be achieved by keeping the
CS4265 in normal stereo mode, and placing consecutive audio samples in the left and right positions in an incoming
96 kHz word rate data stream.
4.13 I²C Control Port Description and Timing
The control port is used to access the registers, allowing the CS4265 to be configured for the desired operational
modes and formats. The operation of the control port may be completely asynchronous with respect to the audio
sample rates. However, to avoid potential interference problems, the control port pins should remain static if no op-
eration is required.
SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. A 47 kΩ pull-up or pull-
down on the SDOUT pin will set AD0, the least significant bit of the chip address. A pull-up to VLS will set AD0 to ‘1’
and a pull-down to DGND will set AD0 to ‘0’. The state of SDOUT is sensed and AD0 is set upon the release of
RESET.
The signal timings for a read and write cycle are shown in Figure 15 and Figure 16. A Start condition is defined as
a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All
other transitions of SDA occur while the clock is low. The first byte sent to the CS4265 after a Start condition consists
of a 7 bit chip address field and a R/W bit (high for a read, low for a write). The upper 6 bits of the 7-bit address field
are fixed at 100111. To communicate with a CS4265, the chip address field, which is the first byte sent to the
CS4265, should match 100111 followed by the setting of AD0. The eighth bit of the address is the R/W bit. If the
operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or
written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto
increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an ac-
knowledge bit. The ACK bit is output from the CS4265 after each input byte is read, and is input to the CS4265 from
the microcontroller after each transmitted byte.
SCL
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 25 26 27 28
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
SDA
1 0 0 1 1 1 AD0 0
INCR 6 5 4 3 2 1 0
76
ACK
ACK
START
10
76
ACK
10
Figure 15. Control Port Timing, I²C Write
DATA +n
76 10
ACK
STOP
28
DS657A2